Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples
http://xilinx.github.io/Vitis_Accel_Examples/
MIT License
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How to log waveform of AIE configuration port #88

Open kkenshin1 opened 1 year ago

kkenshin1 commented 1 year ago

Hi all, I'm running the aie_adder demo in hw_emu flow, and I want to log all signals' waveform when running hw_emu the way I log all waveform is that add below info in xrt.ini

[Emulation] 
user_pre_sim_script=<use pre sim script absolute path>

and my pre-sim.tcl is just log_wave -r *

After running the launch_hw_emu.sh and exit the QEMU, I could find dr_behav.wcfg in my behavior sim folder, and when open it in vivado, I could find the hls and aie interface wave, below is the hls kernel mm2s interface waveform image

Based on above result, I think my workflow is correct

When I open the block design of this project, I find that the S00_AXI is connected to the cips_noc IP, and other *_AXIS is connected to hls kernel, two slave and one master image

Based on AM009 documentation, AIE array has a configuration port, AXI master could write instruction into AIE Tile program memory using this AXI bus, I guess this AXI bus in block design is S00_AXI, so that the PS could config the AIE using this axi bus

However when I check the waveform of this axi bus, there is no data transfer on this bus, and the waveform shows below image

Is this bus port used as aie configuration? how could I know the aie boot mechanism, especially how to config the AIE array, and how to start AIE? is there any doc to describe this?

Another thing is that can I just run PL+AIE without PS code? is it possible to start AIE through PL rather than PS?

Thanks!