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YosysHQ / nextpnr

nextpnr portable FPGA place and route tool
ISC License
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Oassing constraints to nextpnr-himbaechel #1248

Closed janschiefer closed 10 months ago

janschiefer commented 10 months ago

How do I pass physical constraints / pin mappings to nextpnr-himbaechel, for example with Gowin chips ( .cst, .pcf )?

yrabbit commented 10 months ago

Well, just like the examples coming from apicula (cst, I don't know anything about pcf):

https://github.com/YosysHQ/apicula/blob/a4f04e0c481d0ab5feb828a311cca1a76c7b18b6/examples/himbaechel/Makefile.himbaechel#L147

janschiefer commented 10 months ago

Nice!

However, nextpnr-himbaechel now finishes, but fails to find a clock in the design, while nextpnr-gowin synthesizes finishes without a problem ( an recognized the clock ).

led.v:

module led (
    input clk,          // clk input
    input rst_i,        // reset input
    output reg [5:0] led    // 6 LEDS pin
);

reg [23:0] counter;

always @(posedge clk or negedge rst_i) begin
    if (!rst_i)
        counter <= 24'd0;
    else if (counter < 24'd1349_9999)       // 0.5s delay
        counter <= counter + 1'd1;
    else
        counter <= 24'd0;
end

always @(posedge clk or negedge rst_i) begin
    if (!rst_i)
        led <= 6'b101110;
    else if (counter == 24'd1349_9999)       // 0.5s delay
        led[5:0] <= {led[4:0],led[5]};
    else
        led <= led;
end

endmodule

led.cst:

//Part Number: GW1NR-LV9QN88PC6/I5

IO_LOC "clk" 52;
IO_LOC "led[0]" 10;
IO_LOC "led[1]" 11;
IO_LOC "led[2]" 13;
IO_LOC "led[3]" 14;
IO_LOC "led[4]" 15;
IO_LOC "led[5]" 16;
IO_LOC "rst_i" 4;

build-gowin.sh:

#!/bin/bash
rm *.json
rm *.fs
yosys -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog led.v; synth_gowin -json synth.json -top led" 
nextpnr-gowin --json synth.json --write out.json --device GW1NR-LV9QN88PC6/I5 --cst led.cst
gowin_pack -d GW1N-9C -o out.fs out.json

build-himbaechel.sh:

#!/bin/bash
rm *.json
rm *.fs
yosys -D LEDS_NR=6 -D OSC_TYPE_OSC -p "read_verilog led.v; synth_gowin -json synth.json -top led" 
nextpnr-himbaechel --json synth.json --write out.json --device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C --vopt cst=led.cst 
gowin_pack -d GW1N-9C -o out.fs out.json

nextpnr-gowin:

Info: Series:GW1N-9 Device:GW1NR-9 Package:QFN88P Speed:C6/I5

Info: Packing constants..
Info: Packing Shadow RAM..
Info: Packing GSR..
Info: No GSR in the chip base
Info: Packing IOs..
Info: Packing diff IOs..
Info: Packing IO logic..
Info: Packing wide LUTs..
Info: Packing LUT5s..
Info: Packing LUT6s..
Info: Packing LUT7s..
Info: Packing LUT8s..
Info: Packing ALUs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Packing PLLs..
Info: Checksum: 0xe157547f

Info: Device utilisation:
Info:                    VCC:     1/    1   100%
Info:                  SLICE:    92/ 8640     1%
Info:                    IOB:     8/  274     2%
Info:                 OSER16:     0/   38     0%
Info:                 IDES16:     0/   38     0%
Info:                IOLOGIC:     0/  296     0%
Info:              MUX2_LUT5:     2/ 4320     0%
Info:              MUX2_LUT6:     0/ 2160     0%
Info:              MUX2_LUT7:     0/ 1080     0%
Info:              MUX2_LUT8:     0/ 1056     0%
Info:                    GND:     1/    1   100%
Info:                   RAMW:     0/  270     0%
Info:                    OSC:     0/    1     0%
Info:                   rPLL:     0/    2     0%

Info: Placed 8 cells based on constraints.
Info: Creating initial analytic placement for 42 cells, random placement wirelen = 2446.
Info:     at initial placer iter 0, wirelen = 161
Info:     at initial placer iter 1, wirelen = 165
Info:     at initial placer iter 2, wirelen = 163
Info:     at initial placer iter 3, wirelen = 165
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type SLICE: wirelen solved = 165, spread = 343, legal = 401; time = 0.00s
Info:     at iteration #1, type GND: wirelen solved = 401, spread = 401, legal = 401; time = 0.00s
Info:     at iteration #1, type MUX2_LUT5: wirelen solved = 378, spread = 378, legal = 378; time = 0.00s
Info:     at iteration #1, type VCC: wirelen solved = 378, spread = 378, legal = 378; time = 0.00s
Info:     at iteration #1, type ALL: wirelen solved = 167, spread = 332, legal = 405; time = 0.00s
Info:     at iteration #2, type SLICE: wirelen solved = 158, spread = 384, legal = 400; time = 0.00s
Info:     at iteration #2, type GND: wirelen solved = 400, spread = 400, legal = 400; time = 0.00s
Info:     at iteration #2, type MUX2_LUT5: wirelen solved = 383, spread = 383, legal = 386; time = 0.00s
Info:     at iteration #2, type VCC: wirelen solved = 386, spread = 386, legal = 386; time = 0.00s
Info:     at iteration #2, type ALL: wirelen solved = 142, spread = 337, legal = 336; time = 0.00s
Info:     at iteration #3, type SLICE: wirelen solved = 126, spread = 321, legal = 372; time = 0.00s
Info:     at iteration #3, type GND: wirelen solved = 372, spread = 372, legal = 372; time = 0.00s
Info:     at iteration #3, type MUX2_LUT5: wirelen solved = 364, spread = 364, legal = 364; time = 0.00s
Info:     at iteration #3, type VCC: wirelen solved = 364, spread = 364, legal = 364; time = 0.00s
Info:     at iteration #3, type ALL: wirelen solved = 114, spread = 319, legal = 333; time = 0.00s
Info:     at iteration #4, type SLICE: wirelen solved = 125, spread = 296, legal = 312; time = 0.00s
Info:     at iteration #4, type GND: wirelen solved = 312, spread = 312, legal = 312; time = 0.00s
Info:     at iteration #4, type MUX2_LUT5: wirelen solved = 305, spread = 305, legal = 305; time = 0.00s
Info:     at iteration #4, type VCC: wirelen solved = 305, spread = 305, legal = 305; time = 0.00s
Info:     at iteration #4, type ALL: wirelen solved = 117, spread = 288, legal = 305; time = 0.00s
Info:     at iteration #5, type SLICE: wirelen solved = 124, spread = 294, legal = 309; time = 0.00s
Info:     at iteration #5, type GND: wirelen solved = 309, spread = 309, legal = 309; time = 0.00s
Info:     at iteration #5, type MUX2_LUT5: wirelen solved = 305, spread = 305, legal = 305; time = 0.00s
Info:     at iteration #5, type VCC: wirelen solved = 305, spread = 305, legal = 305; time = 0.00s
Info:     at iteration #5, type ALL: wirelen solved = 118, spread = 300, legal = 313; time = 0.00s
Info:     at iteration #6, type SLICE: wirelen solved = 119, spread = 305, legal = 323; time = 0.00s
Info:     at iteration #6, type GND: wirelen solved = 323, spread = 323, legal = 323; time = 0.00s
Info:     at iteration #6, type MUX2_LUT5: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s
Info:     at iteration #6, type VCC: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s
Info:     at iteration #6, type ALL: wirelen solved = 119, spread = 308, legal = 322; time = 0.00s
Info:     at iteration #7, type SLICE: wirelen solved = 119, spread = 286, legal = 296; time = 0.00s
Info:     at iteration #7, type GND: wirelen solved = 296, spread = 296, legal = 296; time = 0.00s
Info:     at iteration #7, type MUX2_LUT5: wirelen solved = 296, spread = 296, legal = 301; time = 0.00s
Info:     at iteration #7, type VCC: wirelen solved = 301, spread = 301, legal = 301; time = 0.00s
Info:     at iteration #7, type ALL: wirelen solved = 121, spread = 306, legal = 317; time = 0.00s
Info:     at iteration #8, type SLICE: wirelen solved = 119, spread = 291, legal = 302; time = 0.00s
Info:     at iteration #8, type GND: wirelen solved = 302, spread = 302, legal = 302; time = 0.00s
Info:     at iteration #8, type MUX2_LUT5: wirelen solved = 298, spread = 298, legal = 298; time = 0.00s
Info:     at iteration #8, type VCC: wirelen solved = 298, spread = 298, legal = 298; time = 0.00s
Info:     at iteration #8, type ALL: wirelen solved = 119, spread = 296, legal = 311; time = 0.00s
Info:     at iteration #9, type SLICE: wirelen solved = 120, spread = 303, legal = 316; time = 0.00s
Info:     at iteration #9, type GND: wirelen solved = 316, spread = 316, legal = 316; time = 0.00s
Info:     at iteration #9, type MUX2_LUT5: wirelen solved = 312, spread = 312, legal = 312; time = 0.00s
Info:     at iteration #9, type VCC: wirelen solved = 312, spread = 312, legal = 312; time = 0.00s
Info:     at iteration #9, type ALL: wirelen solved = 122, spread = 298, legal = 318; time = 0.00s
Info: HeAP Placer Time: 0.04s
Info:   of which solving equations: 0.02s
Info:   of which spreading cells: 0.01s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 22, wirelen = 305
Info:   at iteration #5: temp = 0.000000, timing cost = 14, wirelen = 244
Info:   at iteration #10: temp = 0.000000, timing cost = 34, wirelen = 223
Info:   at iteration #13: temp = 0.000000, timing cost = 34, wirelen = 221 
Info: SA placement time 0.03s

**Info: Max frequency for clock 'clk_IBUF_I_O': 316.86 MHz (PASS at 12.00 MHz)**

Info: Max delay posedge clk_IBUF_I_O -> <async>: 4.46 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 80177,  80292) |********************** 
Info: [ 80292,  80407) | 
Info: [ 80407,  80522) | 
Info: [ 80522,  80637) | 
Info: [ 80637,  80752) | 
Info: [ 80752,  80867) | 
Info: [ 80867,  80982) |* 
Info: [ 80982,  81097) | 
Info: [ 81097,  81212) | 
Info: [ 81212,  81327) | 
Info: [ 81327,  81442) | 
Info: [ 81442,  81557) | 
Info: [ 81557,  81672) | 
Info: [ 81672,  81787) | 
Info: [ 81787,  81902) | 
Info: [ 81902,  82017) | 
Info: [ 82017,  82132) |** 
Info: [ 82132,  82247) | 
Info: [ 82247,  82362) | 
Info: [ 82362,  82477) |***** 
Info: Checksum: 0x29982fdc
Info: Find global nets...
Info: Routing globals...
Info:   Route net clk_IBUF_I_O, use clock #0.
Info:   Net clk_IBUF_I_O is routed.

Info: Routing..
Info: Setting up routing queue.
Info: Routing 314 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        547 |      231        316 |  231   316 |         0|       2.41       2.41|
Info: Routing complete.
Info: Router1 time 2.41s
Info: Checksum: 0xa0be9bd7

Info: Critical path report for clock 'clk_IBUF_I_O' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source clk_IBUF_I_O_DFFC_CLK_23_Q_LUT2_I0_F_LUT2_F_19_LC.Q
Info:  0.5  0.9    Net clk_IBUF_I_O_DFFC_CLK_9_Q[2] (6,15) -> (6,14)
Info:                Sink clk_IBUF_I_O_DFFC_CLK_9_Q_ALU_I1_2_ALULC.B
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.1  2.0  Source clk_IBUF_I_O_DFFC_CLK_9_Q_ALU_I1_2_ALULC.F
Info:  0.8  2.8    Net clk_IBUF_I_O_DFFC_CLK_9_Q_ALU_I1_2_SUM[1] (6,14) -> (6,15)
Info:                Sink clk_IBUF_I_O_DFFC_CLK_23_Q_LUT2_I0_F_LUT2_F_19_LC.B
Info:                Defined in:
Info:                  /usr/local/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.0  2.8  Setup clk_IBUF_I_O_DFFC_CLK_23_Q_LUT2_I0_F_LUT2_F_19_LC.B
Info: 1.6 ns logic, 1.3 ns routing

Info: Critical path report for cross-domain path 'posedge clk_IBUF_I_O' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source clk_IBUF_I_O_DFFCE_CLK_DFFLC.Q
Info:  2.7  3.2    Net led_OBUF_O_I[4] (1,17) -> (0,24)
Info:                Sink led_OBUF_O_1$iob.I
Info: 0.5 ns logic, 2.7 ns routing

**Info: Max frequency for clock 'clk_IBUF_I_O': 352.11 MHz (PASS at 12.00 MHz)**

Info: Max delay posedge clk_IBUF_I_O -> <async>: 3.18 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 80493,  80596) |******** 
Info: [ 80596,  80699) |**** 
Info: [ 80699,  80802) | 
Info: [ 80802,  80905) |*** 
Info: [ 80905,  81008) |******* 
Info: [ 81008,  81111) |* 
Info: [ 81111,  81214) | 
Info: [ 81214,  81317) | 
Info: [ 81317,  81420) | 
Info: [ 81420,  81523) | 
Info: [ 81523,  81626) | 
Info: [ 81626,  81729) | 
Info: [ 81729,  81832) | 
Info: [ 81832,  81935) | 
Info: [ 81935,  82038) | 
Info: [ 82038,  82141) | 
Info: [ 82141,  82244) | 
Info: [ 82244,  82347) | 
Info: [ 82347,  82450) | 
Info: [ 82450,  82553) |******* 

Info: Program finished normally.

nextpnr-himbaechel:

Info: Using uarch 'gowin' for device 'GW1NR-LV9QN88PC6/I5'

Info: Reading constraints...
Info: Create constant nets...
Info: Modify LUTs...
Info: Pack IOBs...
Info: Pack diff IOBs...
Info: Pack IO logic...
Info: Pack DESER16 logic...
Info: Pack GSR..
Info: Pack wide LUTs...
Info: Packed MUX2_LUT8:0, MUX2_LU7:0, MUX2_LUT6:0, MUX2_LUT5:2
Info: Pack ALUs...
Info: Constrained 24 LUTFF pairs.
Info: Pack PLL..
Info: Pack RAMs...
Info: Pack buffered nets..
Info: Checksum: 0xc4c2b9f2

Info: Device utilisation:
Info:                    VCC:     1/    1   100%
Info:                    IOB:     8/  274     2%
Info:                   LUT4:    34/ 8640     0%
Info:                 OSER16:     0/   80     0%
Info:                 IDES16:     0/   80     0%
Info:                IOLOGIC:     0/  276     0%
Info:              MUX2_LUT5:     2/ 4320     0%
Info:              MUX2_LUT6:     0/ 2160     0%
Info:              MUX2_LUT7:     0/ 1080     0%
Info:              MUX2_LUT8:     0/ 1080     0%
Info:                    ALU:    52/ 6480     0%
Info:                    GND:     1/    1   100%
Info:                    DFF:    30/ 6480     0%
Info:              RAM16SDP4:     0/  270     0%
Info:                    GSR:     1/    1   100%
Info:                    OSC:     0/    1     0%
Info:                   rPLL:     0/    2     0%
Info:                   BUFG:     0/   22     0%

Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 43 cells, random placement wirelen = 2061.
Info:     at initial placer iter 0, wirelen = 147
Info:     at initial placer iter 1, wirelen = 162
Info:     at initial placer iter 2, wirelen = 178
Info:     at initial placer iter 3, wirelen = 183
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type ALU: wirelen solved = 183, spread = 214, legal = 340; time = 0.00s
Info:     at iteration #1, type GSR: wirelen solved = 340, spread = 340, legal = 354; time = 0.00s
Info:     at iteration #1, type LUT4: wirelen solved = 311, spread = 313, legal = 314; time = 0.00s
Info:     at iteration #1, type DFF: wirelen solved = 317, spread = 319, legal = 330; time = 0.00s
Info:     at iteration #1, type VCC: wirelen solved = 332, spread = 332, legal = 330; time = 0.00s
Info:     at iteration #1, type GND: wirelen solved = 329, spread = 329, legal = 344; time = 0.00s
Info:     at iteration #1, type MUX2_LUT5: wirelen solved = 323, spread = 323, legal = 323; time = 0.00s
Info:     at iteration #1, type ALL: wirelen solved = 179, spread = 227, legal = 384; time = 0.00s
Info:     at iteration #2, type ALU: wirelen solved = 287, spread = 330, legal = 432; time = 0.00s
Info:     at iteration #2, type GSR: wirelen solved = 432, spread = 432, legal = 432; time = 0.00s
Info:     at iteration #2, type LUT4: wirelen solved = 343, spread = 343, legal = 366; time = 0.00s
Info:     at iteration #2, type DFF: wirelen solved = 345, spread = 348, legal = 357; time = 0.00s
Info:     at iteration #2, type VCC: wirelen solved = 357, spread = 357, legal = 357; time = 0.00s
Info:     at iteration #2, type GND: wirelen solved = 343, spread = 343, legal = 357; time = 0.00s
Info:     at iteration #2, type MUX2_LUT5: wirelen solved = 344, spread = 344, legal = 344; time = 0.00s
Info:     at iteration #2, type ALL: wirelen solved = 177, spread = 261, legal = 379; time = 0.00s
Info:     at iteration #3, type ALU: wirelen solved = 300, spread = 343, legal = 464; time = 0.00s
Info:     at iteration #3, type GSR: wirelen solved = 464, spread = 464, legal = 464; time = 0.00s
Info:     at iteration #3, type LUT4: wirelen solved = 378, spread = 378, legal = 409; time = 0.00s
Info:     at iteration #3, type DFF: wirelen solved = 374, spread = 378, legal = 394; time = 0.00s
Info:     at iteration #3, type VCC: wirelen solved = 394, spread = 394, legal = 394; time = 0.00s
Info:     at iteration #3, type GND: wirelen solved = 381, spread = 381, legal = 394; time = 0.00s
Info:     at iteration #3, type MUX2_LUT5: wirelen solved = 390, spread = 390, legal = 390; time = 0.00s
Info:     at iteration #3, type ALL: wirelen solved = 195, spread = 254, legal = 375; time = 0.00s
Info:     at iteration #4, type ALU: wirelen solved = 285, spread = 307, legal = 426; time = 0.00s
Info:     at iteration #4, type GSR: wirelen solved = 426, spread = 426, legal = 426; time = 0.00s
Info:     at iteration #4, type LUT4: wirelen solved = 344, spread = 344, legal = 371; time = 0.00s
Info:     at iteration #4, type DFF: wirelen solved = 349, spread = 351, legal = 361; time = 0.00s
Info:     at iteration #4, type VCC: wirelen solved = 361, spread = 361, legal = 361; time = 0.00s
Info:     at iteration #4, type GND: wirelen solved = 348, spread = 348, legal = 361; time = 0.00s
Info:     at iteration #4, type MUX2_LUT5: wirelen solved = 347, spread = 347, legal = 347; time = 0.00s
Info:     at iteration #4, type ALL: wirelen solved = 185, spread = 278, legal = 414; time = 0.00s
Info:     at iteration #5, type ALU: wirelen solved = 289, spread = 329, legal = 438; time = 0.00s
Info:     at iteration #5, type GSR: wirelen solved = 438, spread = 438, legal = 438; time = 0.00s
Info:     at iteration #5, type LUT4: wirelen solved = 374, spread = 374, legal = 391; time = 0.00s
Info:     at iteration #5, type DFF: wirelen solved = 356, spread = 362, legal = 368; time = 0.00s
Info:     at iteration #5, type VCC: wirelen solved = 368, spread = 368, legal = 368; time = 0.00s
Info:     at iteration #5, type GND: wirelen solved = 358, spread = 358, legal = 368; time = 0.00s
Info:     at iteration #5, type MUX2_LUT5: wirelen solved = 365, spread = 365, legal = 365; time = 0.00s
Info:     at iteration #5, type ALL: wirelen solved = 202, spread = 283, legal = 410; time = 0.00s
Info:     at iteration #6, type ALU: wirelen solved = 284, spread = 321, legal = 428; time = 0.00s
Info:     at iteration #6, type GSR: wirelen solved = 428, spread = 428, legal = 428; time = 0.00s
Info:     at iteration #6, type LUT4: wirelen solved = 299, spread = 299, legal = 356; time = 0.00s
Info:     at iteration #6, type DFF: wirelen solved = 333, spread = 337, legal = 346; time = 0.00s
Info:     at iteration #6, type VCC: wirelen solved = 346, spread = 346, legal = 346; time = 0.00s
Info:     at iteration #6, type GND: wirelen solved = 344, spread = 344, legal = 346; time = 0.00s
Info:     at iteration #6, type MUX2_LUT5: wirelen solved = 326, spread = 326, legal = 339; time = 0.00s
Info:     at iteration #6, type ALL: wirelen solved = 181, spread = 266, legal = 380; time = 0.00s
Info:     at iteration #7, type ALU: wirelen solved = 280, spread = 323, legal = 380; time = 0.00s
Info:     at iteration #7, type GSR: wirelen solved = 380, spread = 380, legal = 380; time = 0.00s
Info:     at iteration #7, type LUT4: wirelen solved = 316, spread = 316, legal = 335; time = 0.00s
Info:     at iteration #7, type DFF: wirelen solved = 307, spread = 311, legal = 323; time = 0.00s
Info:     at iteration #7, type VCC: wirelen solved = 323, spread = 323, legal = 323; time = 0.00s
Info:     at iteration #7, type GND: wirelen solved = 321, spread = 321, legal = 323; time = 0.00s
Info:     at iteration #7, type MUX2_LUT5: wirelen solved = 313, spread = 313, legal = 313; time = 0.00s
Info:     at iteration #7, type ALL: wirelen solved = 197, spread = 248, legal = 363; time = 0.00s
Info:     at iteration #8, type ALU: wirelen solved = 270, spread = 296, legal = 358; time = 0.00s
Info:     at iteration #8, type GSR: wirelen solved = 358, spread = 358, legal = 358; time = 0.00s
Info:     at iteration #8, type LUT4: wirelen solved = 279, spread = 279, legal = 316; time = 0.00s
Info:     at iteration #8, type DFF: wirelen solved = 305, spread = 310, legal = 319; time = 0.00s
Info:     at iteration #8, type VCC: wirelen solved = 319, spread = 319, legal = 319; time = 0.00s
Info:     at iteration #8, type GND: wirelen solved = 317, spread = 317, legal = 319; time = 0.00s
Info:     at iteration #8, type MUX2_LUT5: wirelen solved = 309, spread = 309, legal = 307; time = 0.00s
Info:     at iteration #8, type ALL: wirelen solved = 179, spread = 220, legal = 340; time = 0.00s
Info:     at iteration #9, type ALU: wirelen solved = 316, spread = 316, legal = 353; time = 0.00s
Info:     at iteration #9, type GSR: wirelen solved = 353, spread = 353, legal = 353; time = 0.00s
Info:     at iteration #9, type LUT4: wirelen solved = 288, spread = 306, legal = 349; time = 0.00s
Info:     at iteration #9, type DFF: wirelen solved = 337, spread = 340, legal = 350; time = 0.00s
Info:     at iteration #9, type VCC: wirelen solved = 350, spread = 350, legal = 350; time = 0.00s
Info:     at iteration #9, type GND: wirelen solved = 348, spread = 348, legal = 350; time = 0.00s
Info:     at iteration #9, type MUX2_LUT5: wirelen solved = 341, spread = 341, legal = 349; time = 0.00s
Info:     at iteration #9, type ALL: wirelen solved = 167, spread = 223, legal = 352; time = 0.00s
Info:     at iteration #10, type ALU: wirelen solved = 285, spread = 307, legal = 365; time = 0.00s
Info:     at iteration #10, type GSR: wirelen solved = 365, spread = 365, legal = 365; time = 0.00s
Info:     at iteration #10, type LUT4: wirelen solved = 283, spread = 281, legal = 321; time = 0.00s
Info:     at iteration #10, type DFF: wirelen solved = 310, spread = 316, legal = 325; time = 0.00s
Info:     at iteration #10, type VCC: wirelen solved = 325, spread = 325, legal = 325; time = 0.00s
Info:     at iteration #10, type GND: wirelen solved = 323, spread = 323, legal = 325; time = 0.00s
Info:     at iteration #10, type MUX2_LUT5: wirelen solved = 325, spread = 325, legal = 325; time = 0.00s
Info:     at iteration #10, type ALL: wirelen solved = 186, spread = 235, legal = 350; time = 0.00s
Info:     at iteration #11, type ALU: wirelen solved = 251, spread = 268, legal = 350; time = 0.00s
Info:     at iteration #11, type GSR: wirelen solved = 350, spread = 350, legal = 350; time = 0.00s
Info:     at iteration #11, type LUT4: wirelen solved = 331, spread = 331, legal = 349; time = 0.00s
Info:     at iteration #11, type DFF: wirelen solved = 334, spread = 341, legal = 354; time = 0.00s
Info:     at iteration #11, type VCC: wirelen solved = 354, spread = 354, legal = 354; time = 0.00s
Info:     at iteration #11, type GND: wirelen solved = 353, spread = 353, legal = 354; time = 0.00s
Info:     at iteration #11, type MUX2_LUT5: wirelen solved = 342, spread = 342, legal = 353; time = 0.00s
Info:     at iteration #11, type ALL: wirelen solved = 185, spread = 218, legal = 343; time = 0.00s
Info:     at iteration #12, type ALU: wirelen solved = 277, spread = 292, legal = 346; time = 0.00s
Info:     at iteration #12, type GSR: wirelen solved = 346, spread = 346, legal = 346; time = 0.00s
Info:     at iteration #12, type LUT4: wirelen solved = 283, spread = 286, legal = 316; time = 0.00s
Info:     at iteration #12, type DFF: wirelen solved = 304, spread = 311, legal = 323; time = 0.00s
Info:     at iteration #12, type VCC: wirelen solved = 323, spread = 323, legal = 323; time = 0.00s
Info:     at iteration #12, type GND: wirelen solved = 322, spread = 322, legal = 323; time = 0.00s
Info:     at iteration #12, type MUX2_LUT5: wirelen solved = 316, spread = 316, legal = 315; time = 0.00s
Info:     at iteration #12, type ALL: wirelen solved = 185, spread = 224, legal = 370; time = 0.00s
Info:     at iteration #13, type ALU: wirelen solved = 252, spread = 273, legal = 370; time = 0.00s
Info:     at iteration #13, type GSR: wirelen solved = 370, spread = 370, legal = 370; time = 0.00s
Info:     at iteration #13, type LUT4: wirelen solved = 337, spread = 337, legal = 357; time = 0.00s
Info:     at iteration #13, type DFF: wirelen solved = 329, spread = 331, legal = 341; time = 0.00s
Info:     at iteration #13, type VCC: wirelen solved = 341, spread = 341, legal = 341; time = 0.00s
Info:     at iteration #13, type GND: wirelen solved = 341, spread = 341, legal = 341; time = 0.00s
Info:     at iteration #13, type MUX2_LUT5: wirelen solved = 338, spread = 338, legal = 338; time = 0.00s
Info:     at iteration #13, type ALL: wirelen solved = 177, spread = 225, legal = 357; time = 0.00s
Info: HeAP Placer Time: 0.12s
Info:   of which solving equations: 0.06s
Info:   of which spreading cells: 0.01s
Info:   of which strict legalisation: 0.01s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 0, wirelen = 340
Info:   at iteration #5: temp = 0.000000, timing cost = 0, wirelen = 314
Info:   at iteration #5: temp = 0.000000, timing cost = 0, wirelen = 314 
Info: SA placement time 0.01s

Info: No Fmax available; no interior timing paths found in design.
Info: Checksum: 0x818f8229
Info: Routing globals...
Info:     routed net 'clk_IBUF_I_O' using global resources

Info: Routing..
Info: Setting up routing queue.
Info: Routing 385 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        391 |        4        334 |    4   334 |         0|       1.48       1.48|
Info: Routing complete.
Info: Router1 time 1.48s
Info: Checksum: 0xc1d2c083

**Info: No Fmax available; no interior timing paths found in design.**

Info: Program finished normally.
yrabbit commented 10 months ago

And the problem is...? Interesting blinking, btw.

https://github.com/YosysHQ/nextpnr/assets/6075465/f1034add-3f71-49e1-be39-2e918a830dcf

janschiefer commented 10 months ago

Ok. So just the determination of fmax is not implemented yet.

Thank you!

blink blink

https://github.com/YosysHQ/nextpnr/assets/29553827/e8fd0eb2-ee17-4f54-9b4e-f6dadbefe988