Closed Ownasaurus closed 1 month ago
Try using just the positive pin, toolchains usually only care about that half.
Try using just the positive pin, toolchains usually only care about that half.
Thanks. Then, my top module would just have one input which would be the proper signal? I wouldn't have to explicitly put the T/+ and C/- signals through an ILVDS primitive?
Thanks!
Then, my top module would just have one input which would be the proper signal?
That's correct.
Thank you very much! It certainly synthesizes this way -- just constraining the T/+ part of the pair and only having one input to my top module. I will not be able to test for data integrity for a few weeks until my custom hardware has arrived. I will re-open or create a new issue if I have any further questions.
Thanks again!
You can check it in the nextpnr GUI. We also do this in Amaranth for a while and it seems to work fine in every case it's been tested.
You can check it in the nextpnr GUI. We also do this in Amaranth for a while and it seems to work fine in every case it's been tested.
Thank you for your advice, whitequark. I had never tried the GUI before! I rebuilt nextpnr with the GUI, and tried to figure out how to use it. Is there a good source of documentation for the GUI?
Anyhow, I I think I figured it out well enough to do some basic analysis. In this test, it looks like it assigned tmds_c to BEL X0/Y44/PIOC. I do not see anything assigned to the corresponding PIOD. Would I expect to see the complement assigned there automatically?
Would I expect to see the complement assigned there automatically?
That's actually a good question, I would assume yes but I've never personally done that before on ECP5.
Would I expect to see the complement assigned there automatically?
That's actually a good question, I would assume yes but I've never personally done that before on ECP5.
Well, I built the soc_versa5g example from the prjtrellis repo. It uses an LVDS clkin. the nextpnr gui shows the same behavior as mine: the T/+ is routed but the C/- is not. So I am going to assume this is a success and working as intended. Thanks again for your assistance. And good luck with your work on amaranth and such! I hope somebody else finds this discussion helpful.
I am trying to use an LVDS differential pair as input. In my .LPF file, I have the following:
However, I unfortunately get the following message:
ERROR: cannot place differential IO at location PIOD
Any idea why this might be happening? I believe F2 and E2 should be appropriate for a differential signal as input. Bank 7, corresponding C/D pins. Am I incorrectly setting the constraints in the LPF file?
(Note the signals are named TMDS but are being converted to the appropriate LVDS logic levels before being passed to the FPGA.)
Thank you very much for your time.