YosysHQ / nextpnr

nextpnr portable FPGA place and route tool
ISC License
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Add out-of-context mode to iCE40 architecture #537

Open JulianKemmerer opened 3 years ago

JulianKemmerer commented 3 years ago

Hello there,

I am trying to get timing data for modules without assigning/requiring IO placement.

For ECP5 out of context has worked great. Can the same be done for iCE40?

I tried nextpnr-ice40 --pcf-allow-unconstrained but still get an error about placement SB_IO: 98/ 96 102% ... ERROR: Unable to find a placement location for cell 'iftrue[18]$sb_io'

Thanks for your time!

Forty-Bot commented 2 years ago

--pcf-allow-unconstrained will place all I/Os on pins, it will just choose the pins for you. This will of course affect the timing, since all the I/Os are brought out to pins. You can use a shift register/xor reduction method to get more accurate timing:

module timing (
    input wire clk,
    input wire in_next,
    output wire out,
);

    reg [63:0] in;
    wire [31:0] arg1, arg2;
    reg [31:0] out_next;
    wire [31:0] result;

    always @(posedge clk) begin
        in <= { in[62:0], in_next };
        out_next <= result;
    end

    assign { arg1, arg2 } = in;

    assign out = ^out_next;

    adder (
        .arg1 (arg1),
        .arg2 (arg2),
        .result (result),
    );
endmodule

module adder (
    input wire [31:0] arg1, arg2,
    output reg [31:0] result,
);

    assign result = arg1 + arg2;
endmodule
JulianKemmerer commented 2 years ago

A good option for sure.

However, in my case this is not for my personal design - but a tool that works with many synthesis+pnr flows. So I was initially very adverse to special casing 'generate a shift register module wrapper thing' in my tool flow just for nextpnr-ice40 since like I mentioned for ECP5 OOC works great. (and similar OOC options are already working for Vivado,Quartus,Lattice tools too).

But Ive found that Efinix Efinity tool does not have a OOC mode - so that adds another special case. Perhaps time to reconsider!