Hi, sry I don't want to annoy you to death but I found another issue with the code generation.
/// Port Module
pub const PORT = struct {
pub const base_address = @intToPtr([*]u8, 0x41008000);
pub const version = "U22102.2.0";
pub const GROUP = @ptrCast(*volatile [2]packed struct {
/// Data Direction
DIR: u32,
/// Data Direction Clear
DIRCLR: u32,
/// Data Direction Set
DIRSET: u32,
/// Data Direction Toggle
DIRTGL: u32,
/// Data Output Value
OUT: u32,
/// Data Output Value Clear
OUTCLR: u32,
/// Data Output Value Set
OUTSET: u32,
/// Data Output Value Toggle
OUTTGL: u32,
/// Data Input Value
IN: u32,
/// Control
CTRL: Mmio(32, packed struct {
/// Input Sampling Mode
SAMPLING: u32,
}),
/// Write Configuration
WRCONFIG: Mmio(32, packed struct {
/// Pin Mask for Multiple Pin Configuration
PINMASK: u16,
/// Peripheral Multiplexer Enable
PMUXEN: u1,
/// Input Enable
INEN: u1,
/// Pull Enable
PULLEN: u1,
reserved0: u1,
reserved1: u1,
reserved2: u1,
/// Output Driver Strength Selection
DRVSTR: u1,
reserved3: u1,
/// Peripheral Multiplexing
PMUX: u4,
/// Write PMUX
WRPMUX: u1,
reserved4: u1,
/// Write PINCFG
WRPINCFG: u1,
/// Half-Word Select
HWSEL: u1,
}),
/// Event Input Control
EVCTRL: Mmio(32, packed struct {
/// PORT Event Pin Identifier 0
PID0: u5,
/// PORT Event Action 0
EVACT0: u2,
/// PORT Event Input Enable 0
PORTEI0: u1,
/// PORT Event Pin Identifier 1
PID1: u5,
/// PORT Event Action 1
EVACT1: u2,
/// PORT Event Input Enable 1
PORTEI1: u1,
/// PORT Event Pin Identifier 2
PID2: u5,
/// PORT Event Action 2
EVACT2: u2,
/// PORT Event Input Enable 2
PORTEI2: u1,
/// PORT Event Pin Identifier 3
PID3: u5,
/// PORT Event Action 3
EVACT3: u2,
/// PORT Event Input Enable 3
PORTEI3: u1,
}),
/// Peripheral Multiplexing
PMUX: [16]Mmio(8, packed struct {
/// Peripheral Multiplexing for Even-Numbered Pin
PMUXE: u4,
/// Peripheral Multiplexing for Odd-Numbered Pin
PMUXO: u4,
}),
/// Pin Configuration
PINCFG: [32]Mmio(8, packed struct {
/// Peripheral Multiplexer Enable
PMUXEN: u1,
/// Input Enable
INEN: u1,
/// Pull Enable
PULLEN: u1,
reserved0: u1,
reserved1: u1,
reserved2: u1,
/// Output Driver Strength Selection
DRVSTR: u1,
padding0: u1,
}),
padding0: u32,
padding1: u32,
padding2: u32,
padding3: u32,
padding4: u32,
padding5: u32,
padding6: u32,
padding7: u32,
//padding8: u32, <-- wrong
//padding9: u32,
//padding10: u32,
//padding11: u32,
//padding12: u32,
//padding13: u32,
//padding14: u32,
//padding15: u32,
//padding16: u32,
//padding17: u32,
//padding18: u32,
}, base_address);
};
The data sheet states that port B is at offset 0x80 from the base address, i.e. after PINCFG we need 0x20 padding bytes but regz has inserted 0x4c bytes in total.
Hi, sry I don't want to annoy you to death but I found another issue with the code generation.
The data sheet states that port B is at offset
0x80from the base address, i.e. afterPINCFGwe need0x20padding bytes but regz has inserted0x4cbytes in total.The register file can be found here.