Closed ekoeppen closed 1 year ago
One regression in the rewrite was the generated system registers for ARM. They would explicitly name a bit position after its interrupt for NVIC registers. Would fixing that regression be enough, or should we still communicate this info regardless?
That sounds reasonable! I'll close this then, I can anyways work around this until the regression is fixed.
There are some use cases where the interrupt indices (interrupt vector numbers) are needed, e.g. when working with the NVIC on Cortex-M chips. The indices could in theory be generated on the application side (or in Microzig) by processing the
VectorTable
structure at comptime, but it seems a bit easier to just generate something likeconst VectorIndices = enum(..) {
right away viaregz
.