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ZigEmbeddedGroup / regz

Generate zig code from ATDF or SVD files for microcontrollers.
MIT License
82 stars 29 forks source link

Add core registers for Cortex M0 and M0+ #86

Closed jacobcpeters closed 1 year ago

jacobcpeters commented 1 year ago

This should at least partially solve issues #27 and #28. I only refactored what was already there because that should be enough for my use case. The generated output looks correct, but I can test it whenever I get some time to go back to my original project.

jacobcpeters commented 1 year ago

If cpu.nvic_prio_bits is missing, there should be an error earlier in the logic. However, I did make the check explicit using the same error as earlier in svd.zig:87

In the check for cpu.vendor_systick_config, as far as I can tell from my searches about XML, the only proper values for an xs:boolean are "true" and "false", both specifically lowercase, as well as "1" and "0". Any other value will return an error for the bad representation.

mattnite commented 1 year ago

CI will dial but that’s just from zig master churn, code looks great to me, thanks!