Open mik1234mc opened 2 years ago
Which branch are you building?
Nvm, I got the repository confused with ZBasic. Okay, let me look through this.
Why the -Wno-LATCH warning? Were you getting a latch warning from somewhere?
Hi Dan,
thank you for bringing this up, it was just a first workaround to solve the following verilator error in picorv32.v (it may be actually error in Verilator not handling properly empty strings) and I forgot to resolve it somehow reasonably:
Vmain___024root__DepSet_h3334316c__0.cpp: In function ‘void Vmain___024root___sequent__TOP__5(Vmain___024root*)’:
Vmain___024root__DepSet_h3334316c__0.cpp:10498:14: error: cannot convert ‘std::string’ {aka ‘std::__cxx11::basic_string<char>’} to ‘QData’ {aka ‘long unsigned int’} in assignment
10498 | std::string("");
| ^~~~~~~~~~
| |
| std::string {aka std::__cxx11::basic_string<char>}
More serious patch would look like in this way:
diff --git a/rtl/Makefile b/rtl/Makefile
index f2b61a1..fe0fc23 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -73,7 +73,7 @@ VERILATOR := verilator
else
VERILATOR := $(VERILATOR_ROOT)/bin/verilator
endif
-VFLAGS = -Wall --MMD -O3 --trace -Mdir $(VDIRFB) $(AUTOVDIRS) -cc
+VFLAGS = -Wall -Wno-TIMESCALEMOD -Wno-UNUSED --MMD -O3 --trace -Mdir $(VDIRFB) $(AUTOVDIRS) -cc
-include make.inc
diff --git a/rtl/picorv/picorv32.v b/rtl/picorv/picorv32.v
index fca6030..86201f2 100644
--- a/rtl/picorv/picorv32.v
+++ b/rtl/picorv/picorv32.v
@@ -697,7 +697,7 @@ module picorv32 #(
`FORMAL_KEEP reg dbg_rs2val_valid;
always @* begin
- new_ascii_instr = "";
+ new_ascii_instr = "default";
if (instr_lui) new_ascii_instr = "lui";
if (instr_auipc) new_ascii_instr = "auipc";
diff --git a/sim/verilated/main_tb.cpp b/sim/verilated/main_tb.cpp
index 3493c02..38290f6 100644
--- a/sim/verilated/main_tb.cpp
+++ b/sim/verilated/main_tb.cpp
@@ -49,6 +49,7 @@
// Looking for string: SIM.INCLUDE
#include "verilated.h"
#include "Vmain.h"
+#include "Vmain___024root.h"
#define BASECLASS Vmain
#include "design.h"
@@ -297,7 +298,7 @@ public:
char *bswapd = new char[len+8];
memcpy(bswapd, &buf[offset], wlen);
byteswapbuf(len>>2, (uint32_t *)bswapd);
- memcpy(&m_core->block_ram[start], bswapd, wlen);
+ memcpy(&m_core->rootp->block_ram[start], bswapd, wlen);
delete bswapd;
// AUTOFPGA::Now clean up anything else
// Was there more to write than we wrote?
Hi zipcpu,
I wanted to simulate zipversa design, but I likely don't have the same verilator version as you. I have Verilator 4.216 2021-12-05 rev v4.216-27-g1de2de4b @ debian11. I needed to do some modifications to make it compile. If someone else is interested, here is the diff:
Regards, Michael