Accelerator Architecture Demonstration

This repository contains a demonstration of an accelerator architecture. The architecture is built around and to support the ECP5 Versa board. It contains support for one Gb Ethernet interface, Flash, a block RAM device, and an internal FFT. The ffttest program can be used to send FFT data to the design, which will be received by the fftmain RISC-V program, and sent to the internal accelerator. Once the FFT has been accomplished, the data will be returned back to the host that requested the processing.

As of this posting, all of these components now work to include the FFT accelerator itself.

The design does not (yet) have support for either the second network port, the PCIe connector, or the SDRAM on board.

Pre-Requisites

To build this design, you will need to first install:

• RISC-V GNU toolchain, to include binutils, GCC, and newlib support
• Yosys
• Project Trellis
• NextPNR for the ECP5
• Verilator
• AutoFPGA
• libELF
• NCurses
• OpenOCD

Build

To adjust the peripherals attached to the design, run make autodata. (This is not necessary in general.)

Then, to build the design, run make from the main directory.

To load the design onto the device once it has been built, run

% openocd -f ecp5-versa.cfg -c "transport select jtag; init; svf rtl/zipversa.svf; exit"

You may need to use sudo to run this command.

Once the design has been loaded onto the board, you may then load software on the board using zipload, such as:

% cd sw/host
% zipload ../rv32/fftmain

You can also interact with the board using the software in the sw/host directory. For example, to run the FFT demo, run:

% ./testfft

License

This project is licensed under the GPL.