acsl-technion / ntl

Networking Template Library for Vivado HLS
BSD 2-Clause "Simplified" License
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ntl — Networking Template Library

ntl is a C++ template library for generating efficient FPGA networking applications with Xilinx Vivado HLS. This is a research prototype; use at your own risk. It is free to use as a whole or in parts. Please cite our FCCM'19 paper "Design Patterns for Code Reuse in HLS Packet Processing Pipelines".

BibTeX @INPROCEEDINGS{8735559, author={H. {Eran} and L. {Zeno} and Z. {István} and M. {Silberstein}}, booktitle={2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, title={Design Patterns for Code Reuse in {HLS} Packet Processing Pipelines}, year={2019}, volume={}, number={}, pages={208-217}, keywords={field programmable gate arrays;high level synthesis;logic design;software libraries;class library;FPGA-based SmartNICs;code reuse;HLS packet processing pipelines;high-level synthesis;high-speed networking applications;UDP stateless firewall;key-value store cache;FPGA circuits;Optimization;Tools;C++ languages;Logic gates;Hardware;Field programmable gate arrays;Data structures;High level synthesis;Design methodology;Networking;Packet processing}, doi={10.1109/FCCM.2019.00036}, ISSN={2576-2613}, month={April},}

Directory structure

Dependencies

ntl has been tested with Xilinx Vivado HLS, and Xilinx Vivado 2018.2, and the evaluation P4 application has been tested with Xilinx SDNet 2018.2.

ntl relies on Boost libraries, and was tested with version 1.54.0.

The C simulation test of the UDP firewall example requires googletest and libpcap.

Building a bitstream for the Innova card requires downloading the SDK from Mellanox. We have used version 2768 of the SDK.