adki gen_amba issues - Githubissues

adki / gen_amba

AMBA bus generator including AXI, AHB, and APB

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Using a SystemVerilog reserved word as a function name

#3 dale40 closed 12 months ago
0
generate the full AHB Slave interface？

#2 abeitian closed 2 years ago
0
gen_amba error when Master=2 and Slave=1

#1 TianyangL opened 4 years ago
1