This project is a senior design / capstone project by several Computer Science students at the University of Kansas (KU) in Lawrence.
With many thanks to Derrick Quinn, who conceived and pitched the idea, as well as Dr. Esam El-Araby and Minyoung Joshua Jeng for their advice and support.
The original goal of this project was to create a core based on the RISC-V ISA, specifically implementing the "V" extension for vector operations in order to better support applications such as machine learning. We began with little to no experience with verilog nor CPU implementations.
While we were all novices to chip design and HDL's, we started out with enthusiasm and hoped to take it all in stride. We encountered our first hurdle when we learned that the grading of the course required us to anticipate and list out all of the steps of development in advance, despite us not yet knowing what steps would be involved in this type of project. This lead to a confused approach, where we wound up listing and completing needless tasks in order to meet grading requirements. That approach earned us near-perfect grades, but ate up valuable time that we otherwise could've spent researching and finding ways to actually progress on the project.
Frustrated, we worked with the TA to figure out a way around the grading of the class, and then started to work on the code seen in the /core/ folder. We:
Our plan was to model and test each component in a separate file, and stitch everything together using Vivado's block design tool. However, we quickly grew frustrated with the fragility and limitations of that tool. We were discouraged when our parts order was filled incorrectly, and again when we learned that one of our team members dropped out of the class.
In the Spring 2023 semester, we reconsidered our goals and targeted a more basic implementation of a RISCV core, making heavy reference to an implementation from @UltraEmbedded. By examining and rewriting that code (our version of it is in the /re/ branch) we learned how to structure the project and implement certain features, such as pipeline control, that we were having trouble with. We are no longer expecting to implement the "V" extension, and will instead focus on getting a barebones RV32IM core to a synthesizable state, programming an FPGA with it, and loading / running an RTOS (any available linux kernel) on it.