= The Tyto Project (Version 2)
The Tyto Project is a collection of open source FPGA designs and IP for retro computing and embedded systems, with an emphasis on VHDL and support for both AMD/Xilinx and Intel/Altera targets.
This repository is incomplete. Work to port all the designs and IP from the https://github.com/amb5l/tyto_project[previous version] is ongoing.
A simpler directory structure is used:
src contains source code for designs and common IP.
build contains makefiles for FPGA builds.
test contains makefiles for simulation testbenches.
doc contains documentation.
submodules contains git submodules.
'''
== FPGA Designs
[cols="10,20,70"] |=== |Name|Supported Boards|Description
|<<./doc/designs/ddr3_test/ddr3_test.adoc#,ddr3_test >> |Digilent{nbsp}Nexys{nbsp}Video, QMTech{nbsp}Wukong |A simple DDR3 SDRAM tester based on https://github.com/jorisvr/vhdl_prng[Joris van Rantwijk's Pseudo Random Number Generator]. Hacks the generated HDL to generate the 200MHz IODELAYCTRL reference clock in the DDR3 IP core MMCM.
|<<./doc/designs/hdmi_tpg/hdmi_tpg.adoc#,hdmi_tpg>> |Digilent{nbsp}Nexys{nbsp}Video, QMTech{nbsp}Wukong |HDMI test pattern generator. Displays a test pattern on an HDMI monitor at various SD and HD TV resolutions. Includes test audio output.
|<<./doc/designs/mb_cb/mb_cb.adoc#,mb_cb>> |Digilent{nbsp}Nexys{nbsp}Video, QMTech{nbsp}Wukong |A MicroBlaze CPU with a character buffer display, supporting 480i60 and 576i50 resolutions.
|<<./doc/designs/mb_cb_ps2/mb_cb_ps2.adoc#,mb_cb_ps2>> |Digilent{nbsp}Nexys{nbsp}Video |The <<./doc/designs/mb_cb/mb_cb.adoc#,mb_cb>> design with an added PS/2 keyboard interface.
|<<./doc/designs/mb_fb/mb_fb.adoc#,mb_fb>> |Digilent{nbsp}Nexys{nbsp}Video, QMTech{nbsp}Wukong |A MicroBlaze CPU with a 24 bpp high resolution graphics frame buffer held in DDR3 SDRAM, with simple demo application based on link:https://github.com/tuupola/hagl[Mike Tuupola's hagl graphics library].
|<<doc/designs/np6532_poc/np6532_poc.adoc#,np6532_poc>> |Digilent{nbsp}Nexys{nbsp}Video, QMTech{nbsp}Wukong, Altera{nbsp}Cyclone{nbsp}V{nbsp}Dev{nbsp}Kit, Terasic{nbsp}DE10-Nano |A proof-of-concept demonstration of the <<doc/common/retro/np65/np65.adoc#,np65>> 6502 compatible CPU core clocked at 32MHz. Runs https://github.com/Klaus2m5/6502_65C02_functional_tests[Klaus Dormann's 6502 functional test] in a loop.
|===
To build an FPGA design, navigate to the board specific subdirectory under build/ and run the make command.
== Simulations
[cols="20,80"] |=== |Name|Description
|<<doc/designs/np6532_functest/np6532_functest.adoc#,np6532_functest>> |A <<doc/common/retro/np65/np65.adoc#,np65>> CPU core running https://github.com/Klaus2m5/6502_65C02_functional_tests[Klaus Dormann's 6502 functional test].
|<<doc/designs/tb_saa5050/tb_saa5050.adoc#,tb_saa5050>> |A https://en.wikipedia.org/wiki/Mullard_SAA5050[SAA5050] teletext character generator.
|<<doc/designs/tb_saa5050d/tb_saa5050d.adoc#,tb_saa5050d>> |Progressive scan (scan doubling) equivalent of <<doc/designs/tb_saa5050/tb_saa5050.adoc#,tb_saa5050>>.
|<<doc/designs/tb_ps2_host/tb_ps2_host.adoc#,tb_ps2_host>> |Testbench for PS/2 host IP.
|<<doc/designs/tb_ps2_to_usbhid/tb_ps2_to_usbhid.adoc#,tb_ps2_to_usbhid>> |Testbench for PS/2 host to USB HID IP.
|<<doc/designs/T65_functest/T65_functest.adoc#,T65_functest>> |A https://github.com/mist-devel/T65[T65 6502 compatible core] running https://github.com/Klaus2m5/6502_65C02_functional_tests[Klaus Dormann's 6502 functional test].
|===
Simulations will normally run on any supported simulator (GHDL, NVC, ModelSim/Questa, Vivado). To run a simulation, navigate to its subdirectory under build/ and run the make command.
== Dependancies
NOTE: ALL designs have submodule dependencies. Please remember to initialise submodules when cloning this repository!
. https://www.gnu.org/software/make/[GNU make], https://www.gnu.org/software/coreutils/[GNU core utilities] and https://git-scm.com/[git] are required. These are normally present on Linux systems. Windows users should use MSYS2 to get these tools running - see <<doc/msys2.adoc#,these notes>> for further details.
. Building an FPGA design requires vendor tools, and produces projects that can be opened and worked on in the vendor's IDE:
For AMD/Xilinx FPGAs, Vivado is required - the free Standard Edition is sufficient. Version since 2020 are supported. Note: designs including a https://en.wikipedia.org/wiki/MicroBlaze[Microblaze soft CPU] require Vitis (this includes Vivado). These tools may be obtained from https://www.xilinx.com/support/download.html[here].
For Intel/Altera FPGAs, Quartus Prime is required - the free Lite edition is sufficient. This includes a free edition of the https://en.wikipedia.org/wiki/ModelSim[Questa] simulator. Versions since 21.1 are supported. Quartus may be obtained from https://www.intel.co.uk/content/www/uk/en/software/programmable/quartus-prime/download.html[here].
. The free open source <<doc/nvc.adoc#,NVC>> and <<doc/ghdl.adoc#,GHDL>> simulators are supported by most simulations. Note that you may need to pre-compile vendor libraries.
. Some builds require https://www.python.org/downloads/[Python 3].
. Projects including a 6502 or compatible CPU require the the ca65 assembler and ld65 linker from the https://cc65.github.io/[cc65] toolchain.
. https://code.visualstudio.com/[Visual Studio Code] is now a supported make target. Run make vscode to build a directory workspace and open the editor. The build process also generates the required config.v4p file for the excellent http://www.vide-software.at/[VHDL for Professionals (V4P)] VS Code extension.
. https://vhdl-style-guide.readthedocs.io/en/latest/[VHDL Style Guide] is supported with a custom configuration file. To fix all source files, run make in the src/ directory.
== License
This file is part of The Tyto Project. The Tyto Project is free software: you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
The Tyto Project is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License along with The Tyto Project. If not, see https://www.gnu.org/licenses/.