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amichai-bd
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rvc_asap
riscv-core-as-simple-as-passible
MIT License
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Instantiate the vga_ctrl under mem_wrap
#48
amichai-bd
closed
2 years ago
0
Make a memory module with standard interface.
#47
amichai-bd
closed
2 years ago
0
Memory change, add 5 tests in C and script enhancment.
#46
gilyaakov
closed
2 years ago
0
Replace Memory module with "standard Interface" memory
#45
amichai-bd
closed
2 years ago
0
Advancing to the next stage đź‘Ť
#44
gilyaakov
closed
2 years ago
0
Add to top level Interface the new FPGA IO (CRs)
#43
amichai-bd
closed
2 years ago
0
Add new Memory Map CR (control registers)
#42
amichai-bd
closed
2 years ago
0
Write 5 new Dedicated Test in 'C'
#41
amichai-bd
closed
2 years ago
2
Fix the build to generate directories that do not exist.
#40
amichai-bd
closed
2 years ago
0
Add "pass" to the Terminal feedback when checking the memory snapshot
#39
amichai-bd
closed
2 years ago
0
Order and organization, data hazard resolution and decode-wb synchronization.
#38
gilyaakov
closed
2 years ago
0
Rename the files belonging to each architecture under the source folder to names with architecture identifiers.
#37
gilyaakov
closed
2 years ago
0
Build hazard detection and forwarding units and reslove data, control and load hazards in the pipelined architecture.
#36
gilyaakov
closed
2 years ago
0
Define new synchronized memory wrapper and fit the pipelined architecture to it.
#35
gilyaakov
closed
2 years ago
0
Gilmatan2
#34
gilyaakov
closed
2 years ago
0
Gilmatan2
#33
matanesh
closed
2 years ago
0
Massive push
#32
gilyaakov
closed
2 years ago
0
fixed golden image of jump_commands.s, updated visio image of the arc…
#31
gilyaakov
closed
2 years ago
0
Edit the design. Imem/Dmem and rvc_core in seprate, rvc_top wrap it all
#30
matanesh
closed
2 years ago
0
Write a quick guide on git (under doc)
#29
amichai-bd
closed
2 years ago
0
Update the README in the source folder
#28
amichai-bd
closed
2 years ago
0
Fix Visio to present the new Hierarchy
#26
amichai-bd
closed
2 years ago
0
Change the hierarchy and split the core from the memory
#25
gilyaakov
closed
2 years ago
0
Gilmatan
#24
gilyaakov
closed
2 years ago
0
Replace tabs in spaces in buildl.sh script & HOW_TO_RUN_BUILDL
#23
gilyaakov
closed
2 years ago
0
After the architecture patches, checking the correctness of complex C code.
#22
gilyaakov
closed
2 years ago
0
Build a test that reads variables from the data memory and to that end build a script that initializes the data memory.
#21
gilyaakov
closed
2 years ago
0
Create a Python script that compares between the "golden_snapshot" to "real_snapshot"
#20
gilyaakov
closed
2 years ago
1
Checking the results of the designated tests and repairing the architecture accordingly.
#19
gilyaakov
closed
2 years ago
1
Gilmatan
#18
gilyaakov
closed
2 years ago
0
finish tests
#17
gilyaakov
closed
2 years ago
0
Add "README" for new folders and scripts.
#16
amichai-bd
closed
2 years ago
0
Add 2 tests, modified buildl.sh script
#15
gilyaakov
closed
2 years ago
0
Change the hierarchy and split the core from the memory
#14
amichai-bd
closed
2 years ago
0
use +define to decide which test you want to run
#13
amichai-bd
closed
2 years ago
0
Continue work on buildl.sh script
#10
gilyaakov
closed
2 years ago
0
Gilmatan
#9
gilyaakov
closed
2 years ago
0
Summary of running 1st program on rvc_asap
#8
matanesh
closed
2 years ago
2
Add addition.c -> compile -> link -> objdump -> objcopy
#7
gilyaakov
closed
2 years ago
0
Write a good HOW_TO for making a "LINKER"
#6
amichai-bd
closed
2 years ago
1
Support the "EBREAK" instruction - make it End the test.
#5
amichai-bd
closed
2 years ago
7
Create dedicated tests for the RV32I ISA
#4
amichai-bd
closed
2 years ago
3
Make <>.f file and compile using modelsim
#3
amichai-bd
closed
3 years ago
0
make the test bench for the RTL - see reference
#2
amichai-bd
closed
3 years ago
0
finish RTL coding (mainly the Ctrl Bits)
#1
amichai-bd
closed
3 years ago
0
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