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antmicro
/
fastvdma
Antmicro's fast, vendor-neutral DMA IP in Chisel
https://antmicro.github.io/fastvdma/
Apache License 2.0
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Porting the fastvdma to Chisel 6 (sbt version)
#24
pznikola
opened
4 months ago
0
will fastvdma support tilelink directly?
#23
SpinEch0
closed
6 months ago
2
Port to Chisel 6.x
#22
kammoh
opened
8 months ago
1
Any example design in Vivado?
#21
nuclearrambo
opened
1 year ago
1
To enable MM2S channel, need to know configurations
#20
kushalc2021
closed
1 year ago
1
Getting error wile running "make test/testall" in master branch
#19
kushalc2021
closed
1 year ago
3
Documentation for use as AXI4 Stream target
#18
p-owens
opened
2 years ago
5
Nit: plural of bus is buses
#17
hughperkins
opened
2 years ago
0
test: Fix reads in AXILite BFM
#16
piotr-binkowski
closed
3 years ago
0
Add info about the linux driver for fastvdma
#15
tgorochowik
closed
3 years ago
0
Trying to change read interface to AXI4, getting elaboration errors when generating verilog
#14
seandextercrevinn
opened
3 years ago
2
doc: add information about CSR fields
#13
piotr-binkowski
closed
3 years ago
0
Documentation for the CSR fields?
#12
seandextercrevinn
closed
3 years ago
1
frontend: axilitecsr: generate read/write CSR signals from AXI ready/valid pairs
#11
piotr-binkowski
closed
3 years ago
0
frontend: add support for frame start notification (axi-stream tuser)
#10
piotr-binkowski
closed
3 years ago
0
test: use big buck bunny frame in full test
#9
piotr-binkowski
closed
3 years ago
0
Wishbone improvements
#8
piotr-binkowski
closed
4 years ago
0
frontend: wishbonecsr rework
#7
piotr-binkowski
closed
4 years ago
1
add support for loop mode
#6
piotr-binkowski
closed
4 years ago
1
README: add register map
#5
piotr-binkowski
closed
4 years ago
1
CSR Memory map
#4
kabrodzki
closed
4 years ago
2
Wishbone config
#3
kabrodzki
closed
4 years ago
1
Is fastvdma tested on rocketchip?
#2
meton-robean
opened
4 years ago
1
Could use a better name
#1
mithro
closed
5 years ago
1