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aolofsson
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oh
Verilog library for ASIC and FPGA designers
MIT License
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Compilation fixes due to latest changes in main
#116
volkamir
closed
8 months ago
0
Create presentation_layout.md
#115
ErArif01
closed
8 months ago
1
Merging master into main
#114
aolofsson
closed
2 years ago
0
Update Readme.md
#113
Intubun
closed
2 years ago
0
Update Readme.md
#112
Intubun
closed
2 years ago
0
Some tweaks to padring library
#111
nmoroze
closed
2 years ago
1
Add "tech config" pass-through for technology-specific GPIO configuration
#110
nmoroze
closed
3 years ago
1
Fix width of padring 'dout' ports
#109
nmoroze
closed
3 years ago
1
Pr aolofsson
#108
aolofsson
closed
3 years ago
0
Consider using sphinx for nice documentation
#107
mithro
opened
4 years ago
0
Open source Xilinx simulation models
#106
mithro
opened
4 years ago
0
Updates
#105
olajep
opened
4 years ago
1
Fixes required for Vivado 2017.4.
#104
hewittc
opened
6 years ago
0
Error when building accelerator example
#103
idlechara
closed
7 years ago
1
fixed typos
#102
wasserfuhr
closed
7 years ago
0
Potential glitch and failure possible in generic_fifo: combinational logic output passed to the other clock domain
#101
pbazarnik
opened
7 years ago
0
Publishing releases
#100
ghost
opened
7 years ago
0
Zcu102
#99
olajep
closed
7 years ago
0
system_bd.tcl Vivado version upgrade gotcha
#98
olajep
opened
7 years ago
2
oh_add: Fix typo in the function description
#97
MattPD
closed
7 years ago
0
Aug fixes
#96
peteasa
closed
8 years ago
1
parallella_accelerator.v missing
#95
jimmysitu
opened
8 years ago
0
fixed sort order
#94
wasserfuhr
closed
7 years ago
0
docs: Fix GPIO description
#93
rnestler
closed
7 years ago
1
Mio driver
#92
olajep
closed
8 years ago
0
Mio fpga
#91
olajep
opened
8 years ago
0
mio: pushback might be broken
#90
olajep
opened
8 years ago
0
mio: need a sticky rx_not_empty bit
#89
olajep
opened
8 years ago
0
oh_fifo_async: GENERIC target probably doesn't synthesize correctly in Vivado
#88
olajep
opened
8 years ago
1
oh_fifo_sync doesn't synthesize properly in Vivado
#87
olajep
opened
8 years ago
0
scripts: build.sh: Enable warnings
#86
olajep
opened
8 years ago
0
Spi cpol0 cpha0
#85
olajep
opened
8 years ago
0
spi: master doesn't transfer 2 MSB in data byte
#84
olajep
opened
8 years ago
1
Spi driver
#83
olajep
opened
8 years ago
0
Parallella oh gpio spi projects separate address space
#82
olajep
closed
8 years ago
0
gpio: Fix issue with new emesh packet format
#81
olajep
closed
8 years ago
0
Elink tx round robin
#80
olajep
opened
8 years ago
0
GPIO: Linux: Support IRQ_TYPE_EDGE_BOTH
#79
olajep
opened
8 years ago
0
SPI fpga project
#78
olajep
closed
8 years ago
1
GPIO: Update Linux driver
#77
olajep
closed
8 years ago
0
GPIO: Fix incorrect documentation for ITYPE register
#76
olajep
closed
8 years ago
0
Gpio fpga project
#75
olajep
closed
8 years ago
0
Gpio fpga project
#74
olajep
closed
8 years ago
1
GPIO: Fix hardcoded address width
#73
olajep
closed
8 years ago
0
esaxi: Explicitly reset timeout counter on reset
#72
olajep
closed
8 years ago
2
GPIO: Update kernel driver
#71
olajep
closed
8 years ago
0
[RFC] GPIO: Change behavior of IMASK
#70
olajep
closed
8 years ago
1
Linux gpio driver
#69
olajep
closed
8 years ago
0
Linux gpio driver
#68
olajep
closed
8 years ago
0
GPIO: Support 32-bit access
#67
olajep
opened
8 years ago
0
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