How to estimate power, area and performance of the eTeak generated circuits?

[Mahdi89]

eTeak as the same as its predecessor counterpart, the Balsa synthesis system, reports area estimation of the generated Verilog circuit. However, this highly depends on the utilised cell library (ASIC/FPGA) and, hence the technology mapping process performed by the tool. Similar to any high-level synthesis tool eTeak/Balsa generated Verilog code can be synthesised using conventional synchronous EDAs such as Synopsys. Thereafter the technology mapped circuits can be simulated for timing analysis and critical path evaluation. You certainly need a harness file for you design at this stage. It is also possible to generate switching activity file (.vcd) for power assessments which is more accurate and realistic than the power estimation techniques performed by the tools based on the circuit models.

[imanazari70]

I have done an asynchronous design, and have achieved its verilog code. Now, I need to do power estimation for my design. I saw in the papers like [1], that Synopsys can be used in this purpose, i.e. it receives also asynchronous verilog code for power analysis. But when I tried synopsys, I realized that it needs input clock for analysis. Then, what should I do? Is there any manual or example that you can refer or provide? .................................................... [1].Oh, Myeong-Hoon, et al. "Architectural Design Issues in a Clockless 32 Bit Processor Using an Asynchronous HDL." ETRI Journal 35.3 (2013): 480-490.

[Mahdi89]

Absolutely and well done on using eTeak, after mapping the design and producing the Verilog netlist you can simply follow the instructions below to drive synopsys: Note that you will need to produce foo.vcd from simulation after tech mapping. you can use vcd2saif from synopsys to convert foo.vcd to foo.saif:

analyze -format verilog elaborate teak_Sorter -architecture verilog -library WORK current_design link saif_map -start compile -exact_map -map_effort medium -area_effort medium read_saif -auto_map_name -instance_name DUT -input foo.saif report_power

[minelpicom]

I have developed my Balsa code, and done the synthesis (including buffering and optimization). Then, I tried to simulate it, and it worked successfully without displaying error message in the terminal. I saw that only the .vcd file contains data. I used this .vcd file to analyze the power consumption of my design. The power analyzer of synopsys responds that ''No switching activity has been annotated''. My insight to this problem is that the vcd file only contains the inputs to the design, and it doesn't contain the outputs. I will appreciate if one provides a start pack for beginners which includes: a sample test in Balsa language, its synthesized version in Verilog, its harness, the outputs files resulted from the simulation (out.dat and report). Then I will be able to track what has caused this problem. Thank you guys in advance.

[Mahdi89]

use vcd2saif of Synopsys to convert your vcd to saif format. (tho It was mentioned in the previous comment)