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ben-marshall
/
uart
A simple implementation of a UART modem in Verilog.
https://ben-marshall.github.io/uart/
MIT License
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Synthesis testing failed.
#6
mayank-kabra2001
opened
1 year ago
2
fix issues on my setup
#5
paulwuertz
closed
3 years ago
0
Issues after checking out
#4
paulwuertz
closed
3 years ago
1
Python 3 support
#3
evanmays
opened
3 years ago
1
Please specify license
#2
motty-mio2
closed
3 years ago
2
Update impl_top.v
#1
gansijuntuan
closed
5 years ago
1