benjamin051000 riscv-business issues - Githubissues

benjamin051000 / riscv-business

A RISC-V RV32I Core

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Ensure all values that are supposed to be sign-extended are

#11 benjamin051000 opened 2 weeks ago
0
HINT instructions

#10 benjamin051000 opened 3 weeks ago
1
Environment Call and Breakpoints

#9 benjamin051000 opened 3 weeks ago
2
Memory Ordering Instructions

#8 benjamin051000 opened 3 weeks ago
0
{L, S}{H, B} implementations

#7 benjamin051000 opened 3 weeks ago
0
Control Transfer Instructions

#6 benjamin051000 opened 3 weeks ago
5
alternate link register?

#5 benjamin051000 opened 3 weeks ago
0
Immediate Encoding Variants (S/B & U/J)

#4 benjamin051000 opened 3 weeks ago
3
generate an exception when jumping to a non-aligned (4-bit alignment) instruction

#3 benjamin051000 opened 3 weeks ago
1
Eventually compile-out flash logic

#2 benjamin051000 opened 2 months ago
0
In datapath.sv, move all declarations to the top.

#1 benjamin051000 closed 2 weeks ago
1