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bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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Port testing directory to make use of FuseSOC #36

Open taylor-bsg opened 5 years ago

taylor-bsg commented 5 years ago

This will allow us to portably build the tests for different verilog simulators so that people can more easily use the tests.

mithro commented 5 years ago

FYI - @olofk

olofk commented 5 years ago

Happy to help out here. Just let me know if you have any questions or seek guidance

taylor-bsg commented 5 years ago

Thanks Olof!

Any suggestions for what components of BaseJump STL should be FuseSOC'd?

It seems like there are two modalities. The first is people using BaseJump STL as a library. The second is people running the regression test on their infrastructure. Currently each test has a configuration for a different tool flow, depending on what the tester had. Of course it would be neat to have FuseSOC abstract that away..

Of course, if you have any cycles to do a proof of concept of setup for our students to follow, that also would be appreciated!

M

On Thu, May 16, 2019 at 12:50 AM Olof Kindgren notifications@github.com wrote:

Happy to help out here. Just let me know if you have any questions or seek guidance

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