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bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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[bsg_fpu] bsg_fpu_cmp make pipeline_p parameter #53

Open tommydcjung opened 5 years ago

tommydcjung commented 5 years ago

pipeline_p=1 : 1-stage pipeline pipeline_p=0 : no pipeline

taylor-bsg commented 5 years ago

Probably should just have no pipeline? The critical path is very short and who is to see whether the user wants the register before or after the logic.

tommydcjung commented 5 years ago

I think I created an issue with wrong title. I meant to say bsg_fpu_f2i. I removed the pipeline to fit it in int-float pipeline. The critical path for f2i is when we are converting floating to two's complement negative int, we have to add 1 at the end. This might be okay, since f2i does not round, but instead truncate.

taylor-bsg commented 5 years ago

Okay we will see if it is critical in the design. It probably was not a path we optimized in Raw.

On Tue, May 28, 2019 at 3:58 PM tommie notifications@github.com wrote:

I think I created an issue with wrong title. I meant to say bsg_fpu_f2i. I removed the pipeline to fit it in int-float pipeline. The critical path for f2i is when we are converting floating to two's complement negative int, we have to add 1 at the end. This might be okay, since f2i does not round, but instead truncate.

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