Open dpetrisko opened 1 year ago
I believe that the changes can be restricted to the bsg_cache_miss.v FSM
I guess the question is how often is TL empty when the cache is in miss. Probably not a common case.
I agree when using bsg_cache as an L2 with cacheline-oriented operations, but this is very common for an L1 with a random access pattern. I discovered this when analyzing the performance of a different cache and using bsg_cache as a reference
Interesting idea, Dan!
When bsg_cache has a miss. it fills the new data and then goes to a "recover" state, where it re-reads tag and data mems in TL. I believe this step can be omitted if v_tl_r == 0, since the memory data in that stage will be unused anyway. This has three major benefits: