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bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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Refactoring bsg_mem_1rw_sync_xxx_subbanked modules #603

Closed KinzaQamar closed 1 year ago

KinzaQamar commented 1 year ago

This PR refactors the modules by

  1. Renaming bsg_mem_1rw_sync_xxx_subbanked to bsg_mem_1rw_sync_xxx_segmented
  2. When num_subbanks_p is 1, the dffs of backing SRAM will latch the reads.
KinzaQamar commented 1 year ago

@dpetrisko does this looks good to you?

KinzaQamar commented 1 year ago

@dpetrisko, changes have been made!

dpetrisko commented 1 year ago

Hi @KinzaQamar, really minor last thing before merging. Can you change num_subbanks_p to num_segments_p?

KinzaQamar commented 1 year ago

Hi @KinzaQamar, really minor last thing before merging. Can you change num_subbanks_p to num_segments_p?

Done! Should be good now.

dpetrisko commented 1 year ago

Awesome thanks!