bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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Adding Verilator Timing Check to bsg_nonsynth_clock_gen #606

Closed stdavids closed 1 year ago

stdavids commented 1 year ago

This also includes some help macros to bsg_defines.v to do some logical and and logical or operations to defined macros.