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bitcraze / lighthouse-fpga

GNU Lesser General Public License v3.0
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Error MAX CLOCK ERROR during the compiling #9

Closed barismetin closed 4 years ago

barismetin commented 4 years ago

Info: Max frequency for clock 'Core_clk': 50.89 MHz (PASS at 48.00 MHz) ERROR: Max frequency for clock 'Slowclk$glb_clk': 23.16 MHz (FAIL at 24.00 MHz)

During the compiling the error above printed. Does anyone know the reason for it?

krichardsson commented 4 years ago

After the FPGA has been built, the resulting design is tested in simulation to make sure it can handle the required clock frequencies. The error you get means that it did not meet the requirements and would only be able to do 23.16 MHz, which is not enough. At this point you have two options:

  1. redesign your changes
  2. change the seed. The build process is randomized but based on a seed, and by changing the seed you will get a different routing with different properties. The current design uses almost all resources in the FPGA and the process when making changes is pretty much to change the seed, rebuild and see if it worked. If not, try another seed and so on. You will find the seed here https://github.com/bitcraze/lighthouse-fpga/blob/V4/Makefile#L20
barismetin commented 4 years ago

Perfect! thank you