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blarney-lang
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pebbles
RISC-V processor framework with plugable pipelines
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Use BRAM to track reg vector status, rather than FFs
#39
mn416
closed
6 months ago
0
Register file leader tweak
#38
mn416
closed
6 months ago
0
Extract stat counter ids into separate .h file
#37
mn416
closed
9 months ago
0
Initial value optimisation
#36
mn416
closed
1 year ago
0
Shared VRF
#35
mn416
closed
1 year ago
0
What is pluggable pipeline?
#34
Honourable-A
opened
1 year ago
3
Shared bounds unit
#33
mn416
closed
1 year ago
0
LRU spill
#32
mn416
closed
1 year ago
0
Dynamic register spill
#31
mn416
closed
1 year ago
0
Scalarised vector store buffer
#30
mn416
closed
2 years ago
0
SIMT twin scalar/vector pipelines
#29
mn416
closed
2 years ago
0
Affine scalarisation
#28
mn416
closed
2 years ago
0
Basic scalarising reg file
#27
mn416
closed
2 years ago
0
Responses in writeback always belong to the same warp
#26
mn416
closed
2 years ago
0
Dot syntax
#25
mn416
closed
2 years ago
0
Warp-preserving in-order banked SRAMs
#24
mn416
closed
2 years ago
0
PCC meta-data divergence implies thread divergence
#23
mn416
closed
2 years ago
0
CHERI support
#22
mn416
closed
3 years ago
0
Exceptions
#21
mn416
closed
3 years ago
0
Tag controller & tag cache
#20
mn416
closed
3 years ago
0
DRAM cache
#19
mn416
closed
3 years ago
0
Restructure: separate SoC from general library
#18
mn416
closed
3 years ago
0
Multi-request atomic transactions
#17
mn416
closed
3 years ago
0
Insert synthesis boundaries for modular compilation
#16
mn416
closed
3 years ago
0
Refactor coalescing unit
#15
mn416
closed
3 years ago
0
Explicit convergence and clang
#14
mn416
closed
3 years ago
0
Measure IPC
#13
mn416
closed
3 years ago
0
Basic SRAM coalescing stage
#12
mn416
closed
3 years ago
0
Fine-grained barrier and CUDA-style grids/blocks
#11
mn416
closed
3 years ago
0
DE10Pro project
#10
mn416
closed
3 years ago
0
Simple atomics optimisation
#9
mn416
closed
3 years ago
0
Banked SRAMs, atomics, barriers
#8
mn416
closed
3 years ago
0
Update DE5-Net project and get Fmax > 200MHz
#7
mn416
closed
3 years ago
0
Synthesis boundary on SIMT execute stage
#6
mn416
closed
3 years ago
0
CPU+SIMT SoC
#5
mn416
closed
3 years ago
0
Simulation framework
#4
mn416
closed
3 years ago
0
Add a .gitignore
#3
gameboo
closed
3 years ago
0
Minor fixes:
#2
gameboo
closed
3 years ago
1
Module restructuring
#1
mn416
closed
3 years ago
0