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brabect1 / zr-soc

RISC-V SoC featuring zero-riscy core.
Apache License 2.0
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How to add the software file? #1

Open 1610Pablo opened 3 years ago

1610Pablo commented 3 years ago

Hi,

I have been trying to do the SoC example for the Arty A7 and I had a problem when it is the time to add the .bram_tcm file. My doubt is how it is possible to attach the software file in the systemVerilog code of the arty_a7_shell.sv? What do you need to change?

Thanks, Pablo

brabect1 commented 3 years ago

Hi Pablo, Sorry for late response. Not sure what exactly your doubt is, but the core idea is that the TCM is simply a HEX dump of the compiled SW binary and the HEX is used to populate the BRAM HDL code. The sample creation of the HEX dump is in zr-soc/fpga/arty-a7/sw/Makefile . Passing the path to the TCM file to the shell SV code is through the TCM_INIT_FILE define; for synthesis/implementation this macro is defined in the Vivado script zr-soc/fpga/arty-a7/scripts/prologue_setup.tcl (coming from an environment variable in zr-soc/fpga/arty-a7/Makefile). Hoping this clarifies enough. Tomas