Closed emonlux closed 1 year ago
What verilog netlist are you using? Verilog port directions on primitives are not defined by default (they need to be specified by defining the architecture or including celldefines for them in the netlist, see spydrnet). Without these ports directions, the adjacency list is not created correctly resulting in no feedback found. This is my first guess at what's happening.
Yeah that fixed the issue.
from spydrnet.util.architecture import XILINX_7SERIES netlist = sdn.parse("netlist.v",architecture = XILINX_7SERIES)
The feedback algorithm does not seem to work for verilog netlists. It does not capture the different layers of feedback in the design that it does for edf netlists.