byuccl / spydrnet-tmr

TMR utilities for the SpyDrNet project

https://byuccl.github.io/spydrnet-tmr/

BSD 3-Clause "New" or "Revised" License

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blif computer-aided-design digital eblif edif electronic-design-automation fpga fpgas hardware-designs netlist netlists spydrnet tmr transformation transformations triple-modular-redundancy verilog

readme

Welcome to SpyDrNet-TMR!

A flexible framework for analyzing and transforming netlists <https://en.wikipedia.org/wiki/Netlist>_. Built to fill an important gap in FPGA research and reliability. Currently available as a pure Python package.

Website and Documentation: https://byuccl.github.io/spydrnet-tmr/

License

Released under the BSD 3-Clause License (see :ref:LICENSE)::