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## Environment
python 3.10, Linux Mint 21, klayout 0.29.5, LVS deck from latest dev branch
## Expected Behavior
LVS passing
## Actual Behavior
LVS failing
## Steps to Reproduce the P…
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Packing Devices from Two Separate Parts of a Netlist into a Single CLB
Hi VTR team,
I merged two netlists into a single BLIF file and used VPR to obtain its design solution on the architecture. Howe…
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I found two circuit environments two-stage and three-stage transimpedance amp., but
could you share more circuit baselines if you have? (e.g. two-stage voltage amplifier or low-dropout regulator)
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We're discussing integration with AutoHoG (see https://www.x-mol.net/paper/article/1761273823319789568).
The authors have a json spec for their optimized circuit output, and we want to enable this …
j2kun updated
4 months ago
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Looking at the [ELK page they have this diagram](https://www.eclipse.org/elk/);
Looking …
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Hi,
I am trying to understand the code. I'm having trouble figuring out how the netlists folder (def/spec/sdc/.v) is used in creating the inputs to the dgl graph. I see no mention of this in the cod…
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Netlists are pretty larges, let's put them here for now while doing the integration tests.
## Netlists:
[NaxRiscvLitex.v-2022-02-08](https://github.com/enjoy-digital/litex_naxriscv_test/files/8030…
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## Expected Behavior
The behavioral/functional Verilog netlists should work in HDL simulation
## Actual Behavior
The behavioral Verilog netlist of High-Density standard cell `stdfrtp` has critica…
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Starting this issue as a tracker where we can keep our ideas and progress.
**Current conclusions**
Yosys can be extremely quick and could be added as a backend for netlist builds. These netlists m…