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### Before start
- [X] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual) and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。
- [X] I have read the […
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I noticed that when running in batch mode even when `verilog-warn-fatal` is set to non-nil, warnings (like unused template lines) are still printed as warnings and not treated as fatal.
Steps to re…
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Clash seems to diverge on the following reproducer (if being called with the `--verilog` flag).
```haskell
-- diverges for: Size > 1
type Size = 2
topEntity :: Bit
topEntity = head table
t…
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We are trying to simulate some simple clockgating blocks that are in verilog. The rest of the design is vhdl.
These seem trivial to convert to VHDL, but the clockgating introduces deltacycle delays o…
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### Discord Thread
https://discord.com/channels/828292123936948244/1309351705074470974
### What happened?
Attempting to change the width of a Verilog output pin to `1` is ignored, `2` seems to be m…
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### Version
0.46
### On which OS did this happen?
Linux
### Reproduction Steps
Read in CVA6 via the [yosys-slang](https://github.com/povik/yosys-slang) plugin and try to write it out again into a…
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**Describe the bug**
Multiplication by constant is not well optimized if output width is the same as arguments' widths. It is possible to write addition with shifts in loop that is faster.
**To Repro…
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There is a Platform config Makefile for Xilinx xrt named platforms.mk, but not for Altera opae. When I try to run opae synthesis in DevCloud, it gives missing DPLATFORM_MEMORY_BANKS, DPLATFORM_MEMORY_…
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`~/cheshire-ihp130-o$ make -B ig-pickle-all fails with below error`
target/ihp13/pickle/out/iguana_chip.morty.sv:181091:10: error: port 'enable_i' does not exist in 'generic_delay_D4_O1_3P750_CG0'
…
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**Describe the bug**
Creating an array of channels and then using it in loop causes internal error.
**To Reproduce**
Steps to reproduce the behavior:
1. Write following code:
```rust
proc Foo {
i…