-
Add support for icarus-verilog & ghdl but check that parallels isn't installed before installing ghdl
-
This can be seen generating .v using the UartCtrlRxMain from the workshop.
it generates multiples cases while one shall be enough.
The code is valid though.
`
always @(*) begin
bitCo…
-
Can you let me know on how to convert system verilog to verilog for yosys
-
The provided simulation Verilog model of CC_PLL isn't a correct representation of the true CC_PLL's behavior. Whatever parameters put in when instantiating CC_PLL get lost and the output clock frequen…
-
There are some duplicate files with alternate casing that collide on case insensitive file systems (default on OSX).
It would be nice if OSX folks and Linux folks saw the same dataset.
```
warn…
-
### Description
I was wondering if mixed language support could be officially added to openlane2.
### Proposal
Openlane2 already has the capability to read in VHDL files using the VHDLClassic…
-
Verible verilog formatter would probably do the trick:
https://google.github.io/verible/verilog_format.html
Likely invocation:
verible-verilog-format /tmp/foo.v --try_wrap_long_lines
-
### Description
I find myself doing this manual navigation a lot:
![image](https://github.com/The-OpenROAD-Project/OpenROAD/assets/2798822/708c1923-8f36-4d28-a6ef-55e2291e4b35)
Ideally I cou…
-
### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
-
**Describe the bug**
When trying to generate Verilog for a fairly complex module written in DSLX the compiler segfaults.
**To Reproduce**
Steps to reproduce the behavior:
- Follow the XL…