veripool verilog-mode issues

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

http://veripool.org/verilog-mode

GNU General Public License v3.0

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issues

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instance ports order is not as delclaration order after set verilog-auto-inst-sort as nil

#1880 WoodsLee1001 closed 2 days ago
1
autowire generate wrong signal width

#1879 younghe1988 closed 2 weeks ago
1
how to get the rest part of instance name?

#1878 zhanjf closed 1 month ago
1
add AUTOLOCAL

#1877 TerrenceSun opened 1 month ago
5
Automatic Port Declaration Sorting in verilog-mode Tool

#1876 1371906755 closed 1 month ago
1
How to except multiple types in recognization (verilog-typedef-regexp)

#1875 szkarn closed 1 month ago
2
Emacs 29: Verilog Mode Font Hilighting: module keyword highlights following label in a comment block.

#1874 dspain55 closed 2 months ago
2
When running xemacs -batch filename -f verilog-batch-auto from command line, I would like the results to have spaces instead of tabs

#1873 longhorngeek closed 2 months ago
1
For .sv files, verilog-mode cannot be recognized in Vim

#1872 1371906755 closed 1 month ago
2
Installation problem

#1871 1371906755 opened 3 months ago
1
This example( \(.*\) ) will result in an error

#1870 1371906755 closed 3 months ago
13
The regular expression .\(.*\) will result in an error if used alone.

#1869 1371906755 closed 3 months ago
6
parameter included in port list when is of user defined type

#1868 lucgozu closed 3 months ago
1
Port alignment issues

#1867 ramyamohandoss closed 3 months ago
1
FAQ not displaying correctly on github

#1866 bcrules82 closed 3 months ago
1
Is there a way to align ports with /*AUTOINST*/ instead of the open parenthesis?

#1865 cswmeta closed 4 months ago
1
import packages not working in emacs.

#1864 deepak00agarwal opened 4 months ago
1
Word select in search stop at underscore

#1863 Diramu closed 4 months ago
3
Module etc. rexexp fixes and cleanup (#1861)

#1862 rlarv closed 4 months ago
1
indentation problem when there is a signal named "module_something"

#1861 rlarv closed 4 months ago
1
Slow with many curly braces (`{`)

#1860 richyliu opened 5 months ago
1
Port Coercion Issue on AUTOINPUT

#1859 ramyamohandoss opened 5 months ago
7
Remove xemacs requirement to build verilog-mode?

#1858 Pinjontall94 closed 5 months ago
2
Typedef struct signals can't be AUTOINPUT(AUTOOUTPUT) generated when AUTOINST

#1857 lucychole closed 5 months ago
1
"package_name::type_t" typed AUTOINST ports do not generate/punch top module ports

#1856 marcink closed 5 months ago
3
fix apostrophe parser in auto wire (#1854)

#1855 anythingelse0 closed 5 months ago
2
autowire/logic on Concatenation operators apostrophe

#1854 anythingelse0 closed 5 months ago
2
how to omit more port when autoinst by regex

#1853 zhanjf closed 5 months ago
2
AUTOLOGIC not decting correct size of multidimension arrays

#1852 amd013 closed 5 months ago
1
typedefs in autooutput

#1851 amd013 closed 5 months ago
2
Add autoinst_multidim_rename test and fix for issue #1848

#1850 techdude closed 6 months ago
1
Do you think it over mixed use with vhdl？

#1849 e665107 closed 6 months ago
1
Multi-Dimensional array template magic [][] substitution fails when original port name matches parent port name, and verilog-auto-inst-vector is off

#1848 techdude closed 6 months ago
3
Using AUTOs with parameterized type

#1847 cswmeta closed 7 months ago
2
How to modify the distance/space/indent of the declaration in the AUTOINPUT/AUTOOUTPUT ？

#1846 szkarn closed 7 months ago
12
make test - fails with message

#1845 nipmac closed 8 months ago
1
Wrong auto extremes computation when signal is connected to input and output

#1844 boorbajones closed 8 months ago
4
Annotations in the AUTO_TEMPLATE

#1843 szkarn closed 9 months ago
1
Remove the modport of the interface from AUTOINST

#1842 szkarn closed 9 months ago
5
How to align the parenthesis generated by autoinst?

#1841 zheBytedance closed 9 months ago
2
Teach AUTOs to process escaped backslashes at the end of quoted strings (#1831)

#1840 acr4 opened 9 months ago
2
RFE: option to have AUTORESET reset flops to `x` rather than `0`

#1839 jwise opened 10 months ago
1
Fix indentation of concurrent properties and sequences (#1836) (#1837)

#1838 acr4 closed 10 months ago
0
Fix indention for cover_sequence_statement

#1837 pbing closed 10 months ago
2
Fix indention for restrict_property_statement

#1836 pbing closed 10 months ago
3
How to make verilog mode not add output for internal signals?

#1835 bharanr closed 10 months ago
3
It there a way to align code inside assigns like follow?

#1834 LeoGitHuber closed 11 months ago
1
verilog-auto-ignore-concat and struct.field fix

#1833 dkatz3c closed 10 months ago
1
Comments added in template can be forwarded to the instantiation?

#1832 rahulrbharadwaj closed 1 year ago
1
Issue when using `\` followed by `"`

#1831 LapinFou opened 1 year ago
3