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I am trying to install on windows and I am getting this issues:
Windows 10
Python 3.11.8
```
Processing c:\git\tmr_tmp
Preparing metadata (setup.py) ... done
Requirement already satisfied: s…
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SpyDrNet is designed to parse in any netlist type, allow for manipulation, and compose any netlist type. However, not all netlist types are treated equally in SpyDrNet. I will use the b13 netlist to i…
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If I have a multi-bit port, how do I distinguish between the various pins?
I have an 8-bit port called *Din*:
When I iterate over the pins they all look identical. I would expect the *InnerPin*…
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Hi all,
I'm pretty much new to this project so I have some questions about it. I hope here is a good place to ask:
1. I can't understand the exact philosophy behind the SpyDrNet. What's different …
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Hi,
When trying to load up a verilog gate netlist written out of Synopsys synthesis tool, I am getting `RecursionError: maximum recursion depth exceeded in comparison`
Below is the code and deta…
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Add RISCV from SpyDrNet to test cases for PyTest.
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SpyDrNet-TMR produces different EDIF netlists from run to run (Python 3.10.4). Repeatability is desirable for traceable builds and automated CAD flows.
For example:
```
netlist = sdn.load_examp…
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There are a lot of files used for examples. It would be nice to create a simple table in a markdown file in the same directory that gives the name, a short description of what the example does, and th…
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I have noticed that there are issues with taking an EBLIF netlist generated by Yosys and using SpyDrNet to transform it into an EDF or Verilog netlist and trying to run the new netlist through Vivado
…
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https://en.wikipedia.org/wiki/EDIF
电子设计互换格式(EDIF)
IEC 61690-2
https://github.com/sinkuu/edif-rs
https://github.com/cisen/edifier-flex-rust
EDIF 分为EDIF netlist和EDIF schematic. EDIF netlist是描述电路网表,…