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I have noticed that there are issues with taking an EBLIF netlist generated by Yosys and using SpyDrNet to transform it into an EDF or Verilog netlist and trying to run the new netlist through Vivado
…
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The [`utils/vpr_pbtype_to_eblif.py`](https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/utils/vpr_pbtype_to_eblif.py) tool currently tries to load a `pb_type.xml` file and generate a suitabl…
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This issue is to keep track of the issue reported here: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1776.
## Problem statement
The auto-generated designs, such as litex, present some…
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# Create a Python library for parsing / producing BLIF (and eBLIF) files
BLIF is the preferred method of design entry for many designers. The Berkeley Logic Interchange Format (BLIF) is a simple fi…
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The vpr_pbtype_to_eblif should support the inbuilt blif model types. The [complete list is found here](https://vtr-verilog-to-routing.readthedocs.io/en/latest/arch/reference.html#pb-type) and listed b…
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Attempting to build docker locally with :
```
docker build . -t symbiflow-ql-slim-buster
```
Fails with :
```
4.3.2. Analyzing design hierarchy..
ERROR: Module `qlal4s3b_cell_macro' referen…
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The latest litex designs do make use of the `FD` primitives which are non other than FDREs with the CE set to one and the R set to 0.
These primitives currently generate errors in the yosys synth s…
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Hi. It seems that both, `pcf` and `xdc` are supported.
I was comparing the three xc7 examples. Taking for example `arty`, I found:
* `counter_test/arty.xdc`
* `linux_litex_demo`:
* `arty.pcf…
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#### Expected Behaviour
Router should route all nets.
#### Current Behaviour
Outputs the warning:
Warning 815554: No routing path found in high-fanout mode for net connection (to sink_rr 125…
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I have followed the instructions in the readme so far but when it comes to loading the bitstream to the Arty A7-100 I get errors.
When I run `./make.py --board=arty --load` i get this error:
`Tr…