This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
Implement Memory Index for IO , so it would be easy to send/receive a stream of data starting at a memory location. Good example would be rs232 Serial UART type data.
Implement Memory Index for IO , so it would be easy to send/receive a stream of data starting at a memory location. Good example would be rs232 Serial UART type data.