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cas-mls / cpu2

This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
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Debug Monitor #10

Open cas-mls opened 10 months ago

cas-mls commented 10 months ago

Need to write code debugging.

  1. Break Instruction
  2. Step Instruction
  3. Display Prog Counter, Registers, Memory.
  4. Modify Prog Counter, Registers, Memory.
  5. No Clue how to interface with it.
  6. Maybe a software interrupt
cas-mls commented 10 months ago

Analysis

It might depend on the wait instructions. Like step...wait and break...wait.

Debugging Technique Description Implementation Test
Single step Allowing the execution of one instruction at a time and observing the contents of registers and memory location after each instruction. Provide an interface to the Computer.
1. Enable it by a switch
2, Single Step on Button Press.
3. Enable CPU using a step/breakpoint special interrupt.		 1. Simulate a signal to stop the program.
2. Simulate the step signal.
Breakpoint Setting breakpoints using the RST instruction and executing the program until the breakpoint. Registers can be examined for the expected result. Maybe insert "swi" to the special step/breakpoint interrupt.
Option 2. Input one single break address and check against Program Counter.		 1. Insert a breakpoint.
Register Examine Examining the contents of the microprocessor register in conjunction with either single-step or breakpoint. Interface to Computer includes the following:
1. Registers
2. Program Counter
3. Instruction
Maybe using the Serial IO. Might change the matrix record to provide output to these items.		 1. Use the Simulation to verify the Registers.