Refactor the Fetch and Decode

cas-mls / cpu2

This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.

MIT License

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Refactor the Fetch and Decode #15

Closed cas-mls closed 4 months ago

cas-mls commented 10 months ago

The Fetch and Decode, I don't think, changes the state of the CPU. It can easily refactored into it own module.

cas-mls commented 4 months ago

This issue was fixed by Issue "Update the software to VHDL 2019+ (ed. VHDL 2008)" #16.