This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
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Update the software to VHDL 2019+ (ed. VHDL 2008) #16
Update the software to ~VHDL 2019+~ VHDL 2008
Learn changes for ~VHDL 2019~ VHDL 2008
Use new/updated ~VHDL 2019~ VHDL 2008 features in the current software.
Also, general cleanup of the code. Vivado put code everywhere. Some in the "new" folder, some in the "import" folder, etc. Also, I suggest working on the *.coe file location and the assembler location.
Should the elements' names be changed to the Ada conventions?
Update the software to ~VHDL 2019+~ VHDL 2008 Learn changes for ~VHDL 2019~ VHDL 2008 Use new/updated ~VHDL 2019~ VHDL 2008 features in the current software.
Also, general cleanup of the code. Vivado put code everywhere. Some in the "new" folder, some in the "import" folder, etc. Also, I suggest working on the *.coe file location and the assembler location.
Should the elements' names be changed to the Ada conventions?