This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
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Implement the RIO and WIO to include Indexed Memory access mode. #17
Produce tests which tests the RIO and WIO. Tested a negative value for the Index. It worked as is, no change.