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cas-mls / cpu2

This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
MIT License
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Create WAIT/TIMER instruction #2

Closed cas-mls closed 5 months ago

cas-mls commented 10 months ago

Need a wait/timer instruction

  1. Need both an asynchronous and synchronous version.
  2. Need to provide an interrupt when the wait is completed.
  3. Need to wait for period of time, or clock cycles.
cas-mls commented 10 months ago

Analyze

  1. The instruction will accept the number of time cycles (32-bits), interrupt number (5-bits), and resolution (16-bits). The total number of clock cycles is time cycles * resolution.
  2. The Register which contains the time cycle will be used and decremented approximately the number of clock cycles of resolution. This allows for multiple waits/timers.
  3. There is a single resolution value. This resolves the problem of keeping the counter in a 32-bit value. But, it is a limitation and the CPU cannot short accurate with a long inaccurate at the same time.
  4. There is a single interrupt number for all of the timers.
  5. Pop Opcode change from 'a' to '9' and Pop has the flag set. Push and Pop are both Opcode 'a'.
  6. Wio Opcode changes from 'c' to 'b' and Wio has the flag set. Rio and Wio are both Opcode 'b'.
  7. Wait/Timer Opcode form R1=Counter, R2=interrupt number, immediate=resolution (0 = 1 clock cycle):
    1. Wait Opcode will be 'aX' with flag=0 and R2=0 (No interrupt)
    2. Timer Opcode will be 'aX' with flag=0 and R2<>0.
    3. Cancel will be opcode 'aX' with flag=1.
  8. Need a flag for each register indicates if the register is used for Nothing 'X', Wait '0', or Timer '1'.
  9. Counter for the number of clock cycles.
  10. When the counter > is indicated by the instruction, then either continue with the next instruction (sync) or call the interrupt handler (async).
  11. Wait until interrupt (infinite wait?)
  12. Cancel Wait Instruction.
  13. Need Infinite Wait, Time=0?
  14. Need tests for sync wait, async wait, cancel, and interrupt timer.
  15. Need a timer test for interrupts going off during wait. Which returns to the rest of the wait.
cas-mls commented 10 months ago

Implementation

  1. Analysis items 2-4, 8 were over-engineered and hard to implement. The implementation includes 1 Wait and 1 Timer and the resolution is unique.
  2. Push/Pop and Rio/Wio rework.
  3. The list of data for each of the timers: 
    signal waitEna : std_logic := '0';
signal waitReg : integer range 0 to 15 := 0;
signal waitTime : unsigned (31 downto 0) := (others => '0');
signal waitCount : unsigned (31 downto 0) := (others => '0');
signal waitResolution : unsigned (15 downto 0) := (others => '0');
signal waitResCounter : unsigned (15 downto 0) := (others => '0');
  4. For the sync (Wait), when counter is going, Wait cycle will be processed. When the counter is finished, the Wait Cycle is stopped and the start of the regular cycle starts.
  5. For the async (timer) the counter is going the regular cycle continues. When the counter is finished the cycle is transferred to the interrupt cycle.
cas-mls commented 5 months ago

Update with addition stuff.