This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
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1. Update to remove the memory IP and put it in the Computer and the … #22
The Timer interrupt return is not working in the simulator, had to remove a 1 cycle wait. That change brakes the hardware. Had to change it back. There is a commented out code around line 444.
…Simulator