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cas-mls / cpu2

This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
MIT License
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16 update the software to vhdl 2019+ ed vhdl 2008 #23

Closed cas-mls closed 4 months ago

cas-mls commented 4 months ago
  1. Update to VHDL 2008.
  2. Fix to work on the real hardware.
  3. Update the finite state model to have 2 process sections: one clocked and the other Combinational.
  4. CPU updated to have process sections for Program Counter, Memory Access, ALU, Wait/Sleep, IO, and Interrupt.
  5. Update to make Modules for each of the process sections.
  6. Fixed the Read Me documentation.