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cas-mls / cpu2

This is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
MIT License
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Fetching the next sequential instruction when executing the current. #5

Closed cas-mls closed 10 months ago

cas-mls commented 10 months ago

Attempt to speed up the processing by fetching the next instruction early for a sequential operation. There are a few reasons to perform this. Fetching the instruction takes 3 clock cycles. I'm using the block memory IP. There might be other IP configurations that could eliminate a few cycles.

There isn't an instruction register. I used the memory as the instruction register. I can do that because the format of all of the instructions is the same. The instruction decode is done in combinational logic. When the memory is updated, the decode will automatically performed. Therefore, the timing would need to be correct.

cas-mls commented 10 months ago

Metric without change (Simultion) 2959 cycles. Set the non-branch to cycle fetch for all memory modes. Simulation 2178 cycles. Set the non-branch to cycle fetch for Absolute and Index, and decode others. Simulation 2152 cycles. 27% Reduction.