I never develop towards the Xtensa based chips, only the C-series riscv boards. So I don't have the custom rustc fork with Xtensa support (the riscv support is built into mainline). Merging this makes it way easier for me to build the examples, as I can just append --target riscv32imc-esp-espidf to my build command and have it work.
I never develop towards the Xtensa based chips, only the
C-series riscv boards. So I don't have the custom rustc fork with Xtensa support (the riscv support is built into mainline). Merging this makes it way easier for me to build the examples, as I can just append--target riscv32imc-esp-espidfto my build command and have it work.