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cepdnaclk
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e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs
This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, and test it on FPGA.
https://cepdnaclk.github.io/e17-4yp-Neuromorphic-NoC-Architecture-for-SNNs/
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web update
#28
Akilax0
closed
11 months ago
0
web update
#27
Akilax0
closed
11 months ago
0
Readme update
#26
Akilax0
closed
11 months ago
0
Add floating point hardware
#25
ImeshBalasuriya
closed
1 year ago
0
Assembler updates
#24
Akilax0
closed
1 year ago
0
assembler /build dir update
#23
Akilax0
closed
1 year ago
0
cleanup unused files
#22
ImeshBalasuriya
closed
1 year ago
0
Code clarity overhaul
#21
ImeshBalasuriya
closed
1 year ago
0
add alu testbench (failing MULHSU!)
#20
ImeshBalasuriya
closed
1 year ago
0
Hazard Detection Unit and minor CPU fixes
#19
ImeshBalasuriya
closed
1 year ago
0
pseudo instructions handling assembler
#18
Akilax0
closed
1 year ago
0
CPU fixes and doc updates
#17
ImeshBalasuriya
closed
1 year ago
0
many CPU fixes
#16
ImeshBalasuriya
closed
1 year ago
0
add missing DIVU and MULH instructions to ALU
#15
ImeshBalasuriya
closed
1 year ago
0
Implement Hazard Detection Unit
#14
ImeshBalasuriya
opened
1 year ago
0
Implement network interface and fifo
#13
Akilax0
closed
1 year ago
0
init
#12
Akilax0
closed
1 year ago
0
Implement FIFO unit
#10
ImeshBalasuriya
opened
1 year ago
0
Implement network interface
#9
ImeshBalasuriya
opened
1 year ago
0
Implement random number generator
#8
ImeshBalasuriya
opened
1 year ago
1
Implement floating point instruction set
#7
ImeshBalasuriya
opened
1 year ago
0
Implement interrupts
#6
ImeshBalasuriya
opened
1 year ago
0
Fix incorrect URL for department website
#5
ImeshBalasuriya
closed
1 year ago
0
update README
#4
ImeshBalasuriya
closed
1 year ago
0
Add abstract section to project page
#3
ImeshBalasuriya
opened
1 year ago
0
Update project README
#2
ImeshBalasuriya
closed
1 year ago
0
update website
#1
ImeshBalasuriya
closed
1 year ago
0