search

chili-chips-ba / openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
https://nlnet.nl/project/TISG
BSD 3-Clause "New" or "Revised" License
25 stars 5 forks source link

Accumulated Cocotb issues/feature requests #10

Closed rmetchev closed 2 months ago

rmetchev commented 6 months ago
  1. Find a reliable alternative to instantiating glbl() in RTL (@chili-chips-ba) image

The same goes here -- RTL should not be burdened with sim modeling code. Instead, that code section should be placed in the behavioral model of ISERDESE2 image

chili-chips-ba commented 6 months ago

Xilinx sim models should be sanitized so that they don't polute log with irrelevant warnings, such as: %Warning-UNDRIVEN: ../../models/no-change/glbl.v:19:10: Signal is not driven: 'p_up_tmp' : ... note: In instance 'top.glbl' 19 | tri1 p_up_tmp; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/UNDRIVEN?v=5.024 ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSEDSIGNAL: ../../models/no-change/glbl.v:20:26: Signal is not used: 'PLL_LOCKG' : ... note: In instance 'top.glbl' 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; | ^~~~~~~~~ %Warning-BLKSEQ: ../../models/no-change/IDELAYCTRL.v:100:16: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 100 | attr_err = 1'b1; | ^ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:124:15: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 124 | clock_edge <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:125:15: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 125 | clock_high <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:126:14: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 126 | clock_low <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:127:9: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 127 | lost <= 1; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:128:11: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 128 | period <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IBUFDS.v:64:39: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 64 | "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; | ^~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.o_out_divide' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.count' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.first_rise' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.half_period_done' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable1' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable2' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable3' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable4' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-BLKSEQ: ../../models/BUFR.v:172:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 172 | ce_enable1 = ce_in; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:173:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 173 | ce_enable2 = ce_enable1; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:174:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 174 | ce_enable3 = ce_enable2; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:175:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 175 | ce_enable4 = ce_enable3; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:220:21: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 220 | o_out_divide = 1'b1; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:221:19: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 221 | first_rise = 1'b0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:224:28: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 224 | o_out_divide = ~o_out_divide; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:225:26: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 225 | half_period_done = 1'b1; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:226:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 226 | count = 0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:229:21: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 229 | o_out_divide = ~o_out_divide; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:230:25: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 230 | half_period_done = 1'b0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:231:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 231 | count = 0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:235:13: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 235 | count = count + 1; | ^ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.o_out_divide' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.count' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.first_rise' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.half_period_done' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable1' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable2' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable3' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable4' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-BLKSEQ: ../../models/IDELAYE2.v:343:32: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 343 | qcntvalueout_reg = 5'b0; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:345:32: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 345 | qcntvalueout_reg = CNTVALUEIN_INTEGER; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:365:68: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 365 | "VAR_LOAD", "VAR_LOAD_PIPE" : idelay_count = qcntvalueout_mux; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:373:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 373 | idelay_count = idelay_count + 1; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:375:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 375 | idelay_count = MIN_DELAY_COUNT; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:383:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 383 | idelay_count = idelay_count - 1; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:385:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 385 | idelay_count = MAX_DELAY_COUNT; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:495:17: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 495 | 0: assign tap_out = delay_chain_0; | ^~~~~~ %Warning-SYNCASYNCNET: /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_top.sv:73:10: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.csi_reset' /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_packer_handler.sv:174:11: ... Location of async usage 174 | if (reset == 1'b1) begin | ^~~~~ /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_align_byte.sv:80:11: ... Location of sync usage 80 | if (reset == 1'b1) begin | ^~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:82:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[0].u_phy_dat.u_indelay.idelay_count' ../../models/IDELAYE2.v:494:15: ... Location of async usage 494 | case (idelay_count) | ^~~~~~~~~~~~ ../../models/IDELAYE2.v:372:45: ... Location of sync usage 372 | if (idelay_count < MAX_DELAY_COUNT) | ^~~~~~~~~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:83:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[0].u_phy_dat.u_indelay.CNTVALUEIN_INTEGER' ../../models/IDELAYE2.v:352:71: ... Location of async usage 352 | "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ ../../models/IDELAYE2.v:345:35: ... Location of sync usage 345 | qcntvalueout_reg = CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:82:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[1].u_phy_dat.u_indelay.idelay_count' ../../models/IDELAYE2.v:494:15: ... Location of async usage 494 | case (idelay_count) | ^~~~~~~~~~~~ ../../models/IDELAYE2.v:372:45: ... Location of sync usage 372 | if (idelay_count < MAX_DELAY_COUNT) | ^~~~~~~~~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:83:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[1].u_phy_dat.u_indelay.CNTVALUEIN_INTEGER' ../../models/IDELAYE2.v:352:71: ... Location of async usage 352 | "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ ../../models/IDELAYE2.v:345:35: ... Location of sync usage 345 | qcntvalueout_reg = CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ %Warning-SYNCASYNCNET: /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/lib/ip/axis_data_fifo.OPENSRC/axis_data_fifo.sv:5:28: Signal flopped as both synchronous and async: 'top.u_rgb2hdmi.__Vcellinp__u_afifo__s_axis_aresetn' /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/lib/ip/axis_data_fifo.OPENSRC/axis_data_fifo.sv:28:11: ... Location of async usage 28 | if (s_axis_aresetn == 1'b0) begin | ^~~~~~~~~~~~~~ /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/lib/ip/axis_data_fifo.OPENSRC/afifo_ctrl.sv:61:11: ... Location of sync usage 61 | if (i_wrst_n == 1'b0) begin | ^~~~~~~~ %Warning-SYNCASYNCNET: ../../models/no-change/IDELAYCTRL.v:64:8: Signal flopped as both synchronous and async: 'top.u_clkrst_gen.u_idelayctrl.RST_in' ../../models/no-change/IDELAYCTRL.v:109:8: ... Location of async usage 109 | if (RST_in == 1'b1) begin | ^~~~~~ ../../models/no-change/IDELAYCTRL.v:133:10: ... Location of sync usage 133 | if(RST_in == 1'b0) begin | ^~~~~~ %Warning-SYNCASYNCNET: /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_clk_det.sv:59:16: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.u_clk_det.byte_clk_fail' /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_clk_det.sv:84:11: ... Location of async usage 84 | if (byte_clk_fail == 1'b1) begin | ^~~~~~~~~~~~~ /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_clk_det.sv:69:16: ... Location of sync usage 69 | else if (byte_clk_fail == 1'b0) begin | ^~~~~~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:84:9: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_posedge' ../../models/no-change/IDELAYCTRL.v:160:4: ... Location of first driving block 160 | clock_posedge <= 1'b1; | ^~~~~~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:149:4: ... Location of other driving block 149 | clock_posedge <= 1'b0; | ^~~~~~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:83:20: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_high' ../../models/no-change/IDELAYCTRL.v:164:4: ... Location of first driving block 164 | clock_high <= 1'b0; | ^~~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:146:4: ... Location of other driving block 146 | clock_high <= 1'b1; | ^~~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:83:9: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_low' ../../models/no-change/IDELAYCTRL.v:165:4: ... Location of first driving block 165 | clock_low <= 1'b1; | ^~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:145:4: ... Location of other driving block 145 | clock_low <= 1'b0; | ^~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:85:9: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.lost' ../../models/no-change/IDELAYCTRL.v:167:8: ... Location of first driving block 167 | lost <= 1'b0; | ^~~~ ../../models/no-change/IDELAYCTRL.v:148:8: ... Location of other driving block 148 | lost <= 1'b0; | ^~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:84:24: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_negedge' ../../models/no-change/IDELAYCTRL.v:168:4: ... Location of first driving block 168 | clock_negedge <= 1'b0; | ^~~~~~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:156:4: ... Location of other driving block 156 | clock_negedge <= 1'b1; | ^~~~~~~~~~~~~

chili-chips-ba commented 6 months ago

'glbl.v' and other Xilinx models should be copied into our project filesystem (e.g. 2.sim/models) and used from there. We cannot assume or expect that everyone would have Xilinx tools installed in the same path, yet alone use the same Vivado version as the one that's hard-coded in our Makefile image

chili-chips-ba commented 6 months ago

image

What exact sim tool (including version) failed to catch this basic syntax error?

rmetchev commented 6 months ago

image

What exact sim tool (including version) failed to catch this basic syntax error?

Fixed. Verilator let that go through.

For record, Verilator 5.024 2024-04-05 rev v5.024-42-gc561fe8ba had detected this issue. image

We need to get to the root of what in cocoTB setup has prevented Verilator from reporting the error that it clearly caught in the standalone setup.

rmetchev commented 6 months ago

'glbl.v' and other Xilinx models should be copied into our project filesystem (e.g. _2.sim/models_) and used from there. We cannot assume or expect that everyone would have Xilinx tools installed in the same path, yet alone use the same Vivado version as the one that's hard-coded in our Makefile image

While copying and "sanitizing" vendor IP is up for debate, we absolutely must agree on tools versions at some point. And in fact, I believe when someone develops for Xilinx FPGAs, we can expect them to have Vivado installed.

There are developers who use Vivado directly from Windows. Others use it from WSL. And some use it from Linux. And, there different versions of Linux, both within WSL and natively. That's too much variety to track.

We already copy and heavily modify a number of Xilinx models. To sanitize them could be as simple as adding Verilator lint_off/on pragmas.

rmetchev commented 6 months ago

Xilinx sim models should be sanitized so that they don't polute log with irrelevant warnings, such as: %Warning-UNDRIVEN: ../../models/no-change/glbl.v:19:10: Signal is not driven: 'p_up_tmp' : ... note: In instance 'top.glbl' 19 | tri1 p_up_tmp; | ^~~~~~~~ ... For warning description see https://verilator.org/warn/UNDRIVEN?v=5.024 ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSEDSIGNAL: ../../models/no-change/glbl.v:20:26: Signal is not used: 'PLL_LOCKG' : ... note: In instance 'top.glbl' 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; | ^~~~~~~~~ %Warning-BLKSEQ: ../../models/no-change/IDELAYCTRL.v:100:16: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 100 | attr_err = 1'b1; | ^ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:124:15: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 124 | clock_edge <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:125:15: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 125 | clock_high <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:126:14: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 126 | clock_low <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:127:9: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 127 | lost <= 1; | ^~ %Warning-INITIALDLY: ../../models/no-change/IDELAYCTRL.v:128:11: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 128 | period <= 0; | ^~ %Warning-INITIALDLY: ../../models/no-change/IBUFDS.v:64:39: Non-blocking assignment '<=' in initial/final block : ... This will be executed as a blocking assignment '='! 64 | "FALSE" : DQS_BIAS_BINARY <= #1 1'b0; | ^~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.o_out_divide' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.count' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.first_rise' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.half_period_done' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable1' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable2' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable3' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_bufr.ce_enable4' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-BLKSEQ: ../../models/BUFR.v:172:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 172 | ce_enable1 = ce_in; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:173:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 173 | ce_enable2 = ce_enable1; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:174:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 174 | ce_enable3 = ce_enable2; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:175:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 175 | ce_enable4 = ce_enable3; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:220:21: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 220 | o_out_divide = 1'b1; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:221:19: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 221 | first_rise = 1'b0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:224:28: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 224 | o_out_divide = ~o_out_divide; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:225:26: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 225 | half_period_done = 1'b1; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:226:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 226 | count = 0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:229:21: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 229 | o_out_divide = ~o_out_divide; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:230:25: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 230 | half_period_done = 1'b0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:231:14: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 231 | count = 0; | ^ %Warning-BLKSEQ: ../../models/BUFR.v:235:13: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 235 | count = count + 1; | ^ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.o_out_divide' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.count' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.first_rise' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.half_period_done' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable1' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable2' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable3' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-LATCH: ../../models/BUFR.v:128:5: Latch inferred for signal 'top.u_csi_rx_top.u_phy_clk.u_clkdiv.ce_enable4' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 128 | always @(gsr_in or clr_in) | ^~~~~~ %Warning-BLKSEQ: ../../models/IDELAYE2.v:343:32: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 343 | qcntvalueout_reg = 5'b0; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:345:32: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 345 | qcntvalueout_reg = CNTVALUEIN_INTEGER; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:365:68: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 365 | "VAR_LOAD", "VAR_LOAD_PIPE" : idelay_count = qcntvalueout_mux; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:373:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 373 | idelay_count = idelay_count + 1; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:375:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 375 | idelay_count = MIN_DELAY_COUNT; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:383:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 383 | idelay_count = idelay_count - 1; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:385:56: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 385 | idelay_count = MAX_DELAY_COUNT; | ^ %Warning-BLKSEQ: ../../models/IDELAYE2.v:495:17: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 495 | 0: assign tap_out = delay_chain_0; | ^~~~~~ %Warning-SYNCASYNCNET: /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_top.sv:73:10: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.csi_reset' /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_packer_handler.sv:174:11: ... Location of async usage 174 | if (reset == 1'b1) begin | ^~~~~ /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_align_byte.sv:80:11: ... Location of sync usage 80 | if (reset == 1'b1) begin | ^~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:82:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[0].u_phy_dat.u_indelay.idelay_count' ../../models/IDELAYE2.v:494:15: ... Location of async usage 494 | case (idelay_count) | ^~~~~~~~~~~~ ../../models/IDELAYE2.v:372:45: ... Location of sync usage 372 | if (idelay_count < MAX_DELAY_COUNT) | ^~~~~~~~~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:83:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[0].u_phy_dat.u_indelay.CNTVALUEIN_INTEGER' ../../models/IDELAYE2.v:352:71: ... Location of async usage 352 | "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ ../../models/IDELAYE2.v:345:35: ... Location of sync usage 345 | qcntvalueout_reg = CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:82:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[1].u_phy_dat.u_indelay.idelay_count' ../../models/IDELAYE2.v:494:15: ... Location of async usage 494 | case (idelay_count) | ^~~~~~~~~~~~ ../../models/IDELAYE2.v:372:45: ... Location of sync usage 372 | if (idelay_count < MAX_DELAY_COUNT) | ^~~~~~~~~~~~ %Warning-SYNCASYNCNET: ../../models/IDELAYE2.v:83:13: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.lane[1].u_phy_dat.u_indelay.CNTVALUEIN_INTEGER' ../../models/IDELAYE2.v:352:71: ... Location of async usage 352 | "FALSE" : always @(CNTVALUEIN_INTEGER) qcntvalueout_mux <= CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ ../../models/IDELAYE2.v:345:35: ... Location of sync usage 345 | qcntvalueout_reg = CNTVALUEIN_INTEGER; | ^~~~~~~~~~~~~~~~~~ %Warning-SYNCASYNCNET: /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/lib/ip/axis_data_fifo.OPENSRC/axis_data_fifo.sv:5:28: Signal flopped as both synchronous and async: 'top.u_rgb2hdmi.__Vcellinp__u_afifo__s_axis_aresetn' /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/lib/ip/axis_data_fifo.OPENSRC/axis_data_fifo.sv:28:11: ... Location of async usage 28 | if (s_axis_aresetn == 1'b0) begin | ^~~~~~~~~~~~~~ /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/lib/ip/axis_data_fifo.OPENSRC/afifo_ctrl.sv:61:11: ... Location of sync usage 61 | if (i_wrst_n == 1'b0) begin | ^~~~~~~~ %Warning-SYNCASYNCNET: ../../models/no-change/IDELAYCTRL.v:64:8: Signal flopped as both synchronous and async: 'top.u_clkrst_gen.u_idelayctrl.RST_in' ../../models/no-change/IDELAYCTRL.v:109:8: ... Location of async usage 109 | if (RST_in == 1'b1) begin | ^~~~~~ ../../models/no-change/IDELAYCTRL.v:133:10: ... Location of sync usage 133 | if(RST_in == 1'b0) begin | ^~~~~~ %Warning-SYNCASYNCNET: /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_clk_det.sv:59:16: Signal flopped as both synchronous and async: 'top.u_csi_rx_top.u_clk_det.byte_clk_fail' /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_clk_det.sv:84:11: ... Location of async usage 84 | if (byte_clk_fail == 1'b1) begin | ^~~~~~~~~~~~~ /mnt/d/Projects/GitHub-repo/openeye-CamSI/1.hw/csi_rx/csi_rx_clk_det.sv:69:16: ... Location of sync usage 69 | else if (byte_clk_fail == 1'b0) begin | ^~~~~~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:84:9: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_posedge' ../../models/no-change/IDELAYCTRL.v:160:4: ... Location of first driving block 160 | clock_posedge <= 1'b1; | ^~~~~~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:149:4: ... Location of other driving block 149 | clock_posedge <= 1'b0; | ^~~~~~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:83:20: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_high' ../../models/no-change/IDELAYCTRL.v:164:4: ... Location of first driving block 164 | clock_high <= 1'b0; | ^~~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:146:4: ... Location of other driving block 146 | clock_high <= 1'b1; | ^~~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:83:9: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_low' ../../models/no-change/IDELAYCTRL.v:165:4: ... Location of first driving block 165 | clock_low <= 1'b1; | ^~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:145:4: ... Location of other driving block 145 | clock_low <= 1'b0; | ^~~~~~~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:85:9: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.lost' ../../models/no-change/IDELAYCTRL.v:167:8: ... Location of first driving block 167 | lost <= 1'b0; | ^~~~ ../../models/no-change/IDELAYCTRL.v:148:8: ... Location of other driving block 148 | lost <= 1'b0; | ^~~~ %Warning-MULTIDRIVEN: ../../models/no-change/IDELAYCTRL.v:84:24: Signal has multiple driving blocks with different clocking: 'top.u_clkrst_gen.u_idelayctrl.clock_negedge' ../../models/no-change/IDELAYCTRL.v:168:4: ... Location of first driving block 168 | clock_negedge <= 1'b0; | ^~~~~~~~~~~~~ ../../models/no-change/IDELAYCTRL.v:156:4: ... Location of other driving block 156 | clock_negedge <= 1'b1; | ^~~~~~~~~~~~~

There are ways to filter out warnings, "sanitizing" vendor IP, esp if not absolutely necessary (ie fatal error) is not one of them, and is a recipe for disaster,

Yes, by wrapping Verilator lint_off/on around them would be sufficient of a sanitizer for this issue.

chili-chips-ba commented 4 months ago

This activity is now transferred to Issue19