issue#4 - Creation of Standalone MMCM Model

[Juninho99]

Creation of Standalone MMCM Model

Description

We need to create a standalone MMCM (Mixed-Mode Clock Manager) model and make some adjustments to the current design by removing the Python parts related to the testbench for the PLL RTL blocks. The following tasks have been identified for this improvement:

Tasks

• [ ] Create a standalone MMCM model using SystemVerilog (SV). The model doesn't need to be complete but should include the minimal functionality required for our use case.
• [ ] Remove the Python parts of the testbench for the PLL RTL blocks and replace them with the actual RTL used for them.

[chili-chips-ba]

That's a good catch!

The current method of modeling at PLL level by direct overrides from cocotb is failing to account for the logic in pll*.sv_ RTL. That results in failing sim, which our earlier DV lead tried to fix by patching RTL for what in reality were modeling issues.