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We need to review the implementation of csi_rx_align_word.sv module.
Modified version, as proposed in the issue#5 branch, works properly in simulation. However, something isn't right for the version that's currently on the main branch.
Below are two waveforms that show the difference.
What we see on the first wave is that valid_out is lined up with word_out, while also filtering out the B8 sync bytes, which is indeed the design intent.
On the second wave however, valid_out is encompassing the B8. That causes downstream failures. Also, few other signals (wait_for_sync, packet_done, etc.) are not looking right in the second wave.
Issue: Review of csi_rx_align_word.sv module
We need to review the implementation of
csi_rx_align_word.sv
module.Modified version, as proposed in the issue#5 branch, works properly in simulation. However, something isn't right for the version that's currently on the main branch.
Below are two waveforms that show the difference.
What we see on the first wave is that![image](https://github.com/chili-chips-ba/openeye-CamSI/assets/70281175/5f8b4294-19b3-4964-bfdb-65b4c2a499ce)
valid_out
is lined up withword_out
, while also filtering out the B8 sync bytes, which is indeed the design intent.On the second wave however,![image](https://github.com/chili-chips-ba/openeye-CamSI/assets/70281175/8426c5a4-1d7f-4733-ac80-388733655c3b)
valid_out
is encompassing the B8. That causes downstream failures. Also, few other signals (wait_for_sync
,packet_done
, etc.) are not looking right in the second wave.