Placement error

[monniaux]

The design does not synthesize.

Version of the FPGA repository: 3b67dc9441f44708b7800ae90c7ef0149e295f72 Version of the swerv_eh1 repository: 48f01f101eeeb8c75013afb4546e01b0fda08984

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_ibufg] >

    ibufg_jtag_tck (IBUF.O) is locked to IOB_X1Y115
     and jtag_tck_ibufg_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

[zhuzhizhan]

The design does not synthesize.

Version of the FPGA repository: 3b67dc9441f44708b7800ae90c7ef0149e295f72 Version of the swerv_eh1 repository: 48f01f101eeeb8c75013afb4546e01b0fda08984

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
  < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_ibufg] >

  ibufg_jtag_tck (IBUF.O) is locked to IOB_X1Y115
   and jtag_tck_ibufg_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Hi， Can someone solve this problem? I run into this problem too.

[zhuzhizhan]

The design does not synthesize. Version of the FPGA repository: 3b67dc9441f44708b7800ae90c7ef0149e295f72 Version of the swerv_eh1 repository: 48f01f101eeeb8c75013afb4546e01b0fda08984

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_ibufg] >

    ibufg_jtag_tck (IBUF.O) is locked to IOB_X1Y115
     and jtag_tck_ibufg_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Hi， Can someone solve this problem? I run into this problem too.

I have added "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck]" to the file and build it well. But the DBG IP did not work well when I tried to connect the device.

[JanMatCodasip]

Hi @zhuzhizhan,

to my knowledge, this Cores-SweRV_fpga repo hasn't been well maintained recently.

Please look at https://github.com/chipsalliance/Cores-SweRVolf for a well-maintained alternative.

Jan