chipsalliance / Cores-SweRV_fpga

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Can not debug with openocd #5

Closed zhuzhizhan closed 3 years ago

zhuzhizhan commented 3 years ago

I use the ft2232hl to debug the core. The cfg is:

JTAG adapter setup

interface ftdi ftdi_vid_pid 0x0403 0x6010 ftdi_channel 1 transport select jtag adapter_khz 1000 ftdi_layout_init 0x00F8 0x00fb ftdi_layout_signal nSRST -oe 0x0040 ftdi_layout_signal ntRST -oe 0x0010 set _CHIPNAME riscv

jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x01

set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME

riscv set_prefer_sba on

init halt

flash protect 0 64 last off

echo "Now, you can connect GDB..."

Execute "openicd -f swerv.cfg", then the log is follow: Open On-Chip Debugger 0.10.0+dev-00849-gcbb15587d (2020-09-10-11:59) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Info : clock speed 1000 kHz Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (), part: 0x0000, ver: 0x0) Error: Debug Module did not become active. dmcontrol=0x0 Info : Listening on port 3333 for gdb connections Error: Target not examined yet

What's the problem?